ICL7129 Datasheet, PDF (5/11 Pages) Intersil Corporation – 41/2 Digit LCD, Single-Chip A/D Converter

ICL7129
Detailed Description
The ICL7129 is a uniquely designed single chip A/D converter.
It features a new “successive integration” technique to achieve
10µV resolution on a 200mV full-scale range. To achieve this
resolution a 10:1 improvement in noise performance over
previous monolithic CMOS A/D converters was accomplished.
Previous integrating converters used an external capacitor to
store an offset correction voltage. This technique worked well
but greatly increased the equivalent noise bandwidth of the
converter. The ICL7129 removes this source of error (noise) by
not using an auto-zero capacitor. Offsets are cancelled using
digital techniques instead. Savings in external parts cost are
realized as well as improved noise performance and elimination
of a source of electromagnetic and electrostatic pick-up.
In the overall Functional Block Diagram of the ICL7129 the
heart of this A/D converter is the sequence counter/decoder
which drives the control logic and keeps track of the many
separate phases required for each conversion cycle. The
sequence counter is constantly running and is a separate
counter from the up/down results counter which is activated
only when the integrator is de-integrating. At the end of a con-
version the data remaining in the results counter is latched,
decoded and multiplexed to the liquid crystal display.
The analog section block diagram shown in Figure 1
includes all of the analog switches used to configure the volt-
age sources and amplifiers in the different phases of the
cycle. The input and reference switching schemes are very
similar to those in other less accurate integrating A/D con-
verters. There are 5 basic configurations used in the full con-
version cycle. Figure 2 illustrates a typical waveform on the
integrator output. INT, INT₁, and INT₂ all refer to the signal
integrate phase where the input voltage is applied to the
integrator amplifier via the buffer amplifier. In this phase, the
integrator ramps over a fixed period of time in a direction
opposite to the polarity of the input voltage.
DE₁, DE₂, and DE₃ are the de-integrate phases where the
reference capacitor is switched in series with the buffer ampli-
fier and the integrator ramps back down to the level it started
from before integrating. However, since the de-integrate phase
can terminate only at a clock pulse transition, there is always a
small overshoot of the integrator past the starting point. The
ICL7129 amplifies this overshoot by 10 and DE₂ begins. Simi-
larly
end
DE₂’s overshoot is amplified by 10
of DE3 the results counter holds a
naunmd bDeEr³wbitehg5in^1s/.₂^Adtigthites
of resolution. This was obtained by feeding counts into the
results counter at
digit level during
the 3¹/₂ digit
DE₂ and the
level
5¹/₂
during DE₁, into the
digit level for DE₃.
4¹/₂
The
effects of offset in the buffer, integrator, and comparator can
now be cancelled by repeating this entire sequence with the
inputs shorted and subtracting the results from the original
reading. For this phase INT₂ switch is closed to give the same
common-mode voltage as the measurement cycle. This
assures excellent CMRR. At the end of the cycle the data in the
up/down results counter is accurate to 0.02% of full scale and is
sent to the display driver for decoding and multiplexing.
C_REF
R_INT
C_INT
REF HI REF LO
BUFFER INT, IN
INT OUT
DE DE
IN HI
INT₁
DE-
COMMON
IN LO
DE+
INT₁, INT₂
-
+
DE+
BUFFER
Z1, X10
DE-
INT
REST, INT₂
10
-
+
100
INTEGRATOR
X10
COMPARATOR 1
+
-
+_-
TO DIGITAL
SECTION
COMPARATOR 2
FIGURE 1. ANALOG BLOCK DIAGRAM
ZERO-INTEGRATE
AND LATCH
INT₁
INTEGRATE
DE₁
DE-INTEGRATE REST X10 DE₂ REST X10 DE₃ ZERO-INTEGRATE
NOTE: Shaded area greatly expanded
in time and amplitude.
1000 CLOCKS
10,000 CLOCKS
2000
CLOCKS
INTEGRATOR
RESIDUE
VOLTAGE
1000 CLOCKS
FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND
RESIDUE VOLTAGE
3-35