HD-15531_02 Datasheet, PDF (6/16 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-15531
ting the decoded data through SERIAL DATA OUT. The
decoded data available at SERIAL DATA OUT is in NRZ
format. The DECODER SHIFT CLOCK is provided so that
the decoded bits can get shifted into an external register on
every low-to-high transition of this clock 2 - 3 . Note that
DECODER SHIFT CLOCK may adjust its phase up until the
time that TAKE DATA goes high.
After all K decoded bits have been transmitted 3 the data is
checked for parity. A high input on DECODER PARITY
SELECT will set the Decoder to check for even parity or a
low input will set the Decoder to check for odd parity. A high
on VALID WORD output 4 indicates a successful reception
of a word without any Manchester or parity errors. At this
time the Decoder is looking for a new sync character to start
another output sequence. VALID WORD will go low approx-
imately K + 4 DECODER SHIFT CLOCK periods after it
goes high, if not reset low sooner by a valid sync and two
valid Manchester bits as shown 1 .
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
TIMING
SYNCHRONOUS
CLOCK
DECODER
SHIFT
CLOCK
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
0
1
2
3
4
5
6
7
8
N-3 N-2 N-1 N
1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5
BIT 3 BIT 2 BIT 1 PARITY
SYNC
SYNC MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5
BIT 3 BIT 2 BIT 1 PARITY
TAKE DATA
COMMAND
SYNC
DATA SYNC
SERIAL
DATA OUT
UNDEFINED
MSB BITK-1 BITK-2 BITK-3
(MAY BE HIGH FROM PREVIOUS RECEPTION)
VALID WORD
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
12
FIGURE 2. DECODER
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