HD-15531_02 Datasheet, PDF (5/16 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-15531
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK. The frame length is set by pro-
gramming the COUNT inputs. Parity is selected by
programming ENCODER PARITY SELECT high for odd par-
ity or low for even parity.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK 1 .
This cycle lasts for one word length or K + 4 ENCODER
SHIFT CLOCK periods, where K is the number of bits to be
sent. At the next low-to-high transition of the ENCODER
SHIFT CLOCK, a high SYNC SELECT input actuates a
Command sync or a low will produce a Data sync for the
word 2 . When the Encoder is ready to accept data, the
SEND DATA output will go high for K ENCODER SHIFT
CLOCK periods 4 . During these K periods the data should
be clocked into the SERIAL DATA input with every high-to-
low transition of the ENCODER SHIFT CLOCK 3 - 4 so it
can be sampled on the low-to-high transition. After the sync
and Manchester II encoded data are transmitted through the
BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
adds on an additional bit with the parity for that word 5 . If
ENCODER ENABLE is held high continuously, consecutive
words will be encoded without an interframe gap.
ENCODER ENABLE must go low by time 5 (as shown) to
prevent a consecutive word from being encoded. At any time
a low on OUTPUT INHIBIT input will force both bipolar out-
puts to a high state but will not affect the Encoder in any
other way.
To abort the Encoder transmission, a positive pulse must be
applied at MASTER RESET. Any time after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
TIMING
0
1
2
3
4
5
6
7
N-4 N-3 N-2 N-1 N
SEND CLOCK
ENCODER
SHIFT CLOCK
ENCODER
ENABLE
SYNC
SELECT
SEND
DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
VALID
DON’T CARE
DON’T CARE
MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5 BIT 4 BIT 3 BIT 2 BIT 1
1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4
SYNC
SYNC MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4
BIT 4 BIT 3 BIT 2 BIT 1 PARITY
BIT 4 BIT 3 BIT 2 BIT 1 PARITY
12
3
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FIGURE 1. ENCODER
Decoder Operation
To operate the Decoder asynchronously requires a single
clock with a frequency of 12 times the desired data rate
applied at the DECODER CLOCK input. To operate the
Decoder synchronously requires a SYNCHRONOUS
CLOCK at a frequency 2 times the data rate which is syn-
chronized with the data at every high-to-low transition
applied to the SYNCHRONOUS CLK input. The Manchester
II coded data can be presented to the Decoder asynchro-
nously in one of two ways. The BIPOLAR ONE and
BIPOLAR ZERO inputs will accept data from a comparator
sensed transformer coupled bus as specified in Military Spec
1553. The UNIPOLAR DATA input can only accept nonin-
verted Manchester II coded data. (e.g., from BIPOLAR ONE
OUT on an Encoder through an inverter to Unipolar Data
Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized 1 , the type of sync is indicated by a high
level at either COMMAND SYNC or DATA SYNC output. If
the sync character was a command sync the COMMAND
SYNC output will go high 2 and remain high for K SHIFT
CLOCK periods 3 , where K is the number of bits to be
received. If the sync character was a data sync, the DATA
SYNC output will go high. The TAKE DATA output will go
high and remain high 2 - 3 while the Decoder is transmit-
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