HD-15531_02 Datasheet, PDF (3/16 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-15531
DECODER
SYNCHRONOUS ⁷
8
DATA SELECT
UNIPOLAR 13
DATA IN
BIPOLAR ¹²
ONE IN
BIPOLAR ¹¹
ONE IN
TRANSITION
FINDER
DATA
SELECT
GATE
DECODER
CLK
DECODER
CLK SELECT
SYNCHRONOUS
CLK
SYNCHRONOUS
CLK SELECT
MASTER
RESET
9
15 ^SYNCHRONIZER
8
10
22
CLOCK
SELECT
DATA
SYNCHRONOUS
DATA
4
CHARACTER 17
IDENTIFIER
BIT
RATE
CLK
5
2
PARITY
CHECK
16
14
TAKE DATA
COMMAND SYNC
DATA SYNC
SERIAL
DATA OUT
VALID WORD
PARITY
SELECT
DECODER
SHIFT CLK
DECODER ¹⁹
RESET
BIT
COUNTER
3
TAKE DATA’
20 40 23 36 39
C₀ C₁ C₂ C₃ C₄
Pin Description
PIN
NUMBER TYPE
NAME
SECTION
DESCRIPTION
1
V_CC
Both
Positive supply pin. A 0.1µF decoupling capacitor from V_CC (pin 1) to GROUND
(pin 21) is recommended.
2
O VALID WORD
Decoder Output high indicates receipt of a valid word, (valid parity and no Manchester
errors).
3
O TAKE DATA’
Decoder
A continuous, free running signal provided for host timing or data handling. When
data is present on the bus, this signal will be synchronized to the incoming data
and will be identical to TAKE DATA.
4
O TAKE DATA
Decoder Output is high during receipt of data after identification of a valid sync pulse and
two valid Manchester bits.
5
O SERIAL DATA OUT Decoder Delivers received data in correct NRZ format.
6
I SYNCHRONOUS
Decoder Input presents Manchester data directly to character identification logic.
DATA
SYNCHRONOUS DATA SELECT must be held high to use this input. If not
used, this pin must be held high.
7
I SYNCHRONOUS
Decoder In high state allows the synchronous data to enter the character identification
DATA SELECT
logic. Tie this input low for asynchronous data.
8
I SYNCHRONOUS
Decoder Input provides externally synchronized clock to the decoder, for use when re-
CLOCK
ceiving synchronous data. This input must be tied high when not in use.
9
I DECODER CLOCK Decoder Input drives the transition finder, and the synchronizer which in turn supplies the
clock to the balance of the decoder. Input a frequency equal to 12X the data rate.
10
I SYNCHRONOUS
Decoder In high state directs the SYNCHRONOUS CLOCK to control the decoder char-
CLOCK SELCT
acter identification logic. A low state selects the DECODER CLOCK.
11
I BIPOLAR ZERO IN Decoder A high input should be applied when the bus is in its negative state. This pin must
be held high when the unipolar input is used.
12
I BIPOLAR ONE IN
Decoder A high input should be applied when the bus is in its positive state. This pin must
he held low when the unipolar input is used.
13
I UNIPOLAR DATA IN Decoder With pin 11 high and pin 12 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
3