HD-15531_02 Datasheet, PDF (12/16 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-15531
AC Electrical Specifications V_CC = 5V ±10%, T_A = -40^oC to +85^oC (HD-15530-9)
T_A = -55^oC to +125^oC (HD-15530-8)
HD-15531
HD-15531B
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX UNITS
ENCODER TIMING
TEST CONDITIONS (NOTE 2)
FEC Encoder Clock Frequency
FESC Send Clock Frequency
FED Encoder Data Rate
TMR Master Reset Pulse Width
TE1 Shift Clock Delay
TE2 Serial Data Setup
TE3 Serial Data Hold
TE4 Enable Setup
TE5 Enable Pulse Width
TE6 Sync Setup
TE7 Sync Pulse Width
TE8 Send Data Delay
TE9 Bipolar Output Delay
TE10 Enable Hold
TE11 Sync Hold
DECODER TIMING
-
15
-
30
MHz V_CC = 4.5V and 5.5V, C_L = 50pF
-
2.5
-
5.0
MHz V_CC = 4.5V and 5.5V, C_L = 50pF
-
1.25
-
2.5
MHz V_CC = 4.5V and 5.5V, C_L = 50pF
150
-
150
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
-
125
-
80
ns V_CC = 4.5V and 5.5V, C_L = 50pF
75
-
50
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
75
-
50
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
90
-
90
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
100
-
100
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
55
-
55
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
150
-
150
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
0
50
0
50
ns V_CC = 4.5V and 5.5V, C_L = 50pF
-
130
-
130
ns V_CC = 4.5V and 5.5V, C_L = 50pF
10
-
10
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
95
-
95
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
FDC Decoder Clock Frequency
-
15
-
30
FDS Decoder Sync Clock
-
2.5
-
5.0
FDD Decoder Data Rate
-
1.25
-
2.5
TDR Decoder Reset Pulse Width
150
-
150
-
TDRS Decoder Reset Setup Time
75
-
75
-
TDRH Decoder Reset Hold Time
10
-
10
-
TMR Master Reset Pulse
150
-
150
-
TD1 Bipolar Data Pulse Width
TDC + 10
-
TDC + 10
-
(Note 1)
(Note 1)
MHz
MHz
MHz
ns
ns
ns
ns
ns
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
V_CC = 4.5V and 5.5V, C_L = 50pF
TD3 One Zero Overlap
-
TDC - 10
-
TDC - 10 ns V_CC = 4.5V and 5.5V, C_L = 50pF
(Note 1)
(Note 1)
TD6
TD7
TD8
TD9
TD10
TD11
TD12
Sync Delay (ON)
Take Data Delay (ON)
Serial Data Out Delay
Sync Delay (OFF)
Take Data Delay (OFF)
Valid Word Delay
Sync Clock to Shift Clock
Delay
-20
110
-20
110
ns V_CC = 4.5V and 5.5V, C_L = 50pF
0
110
0
110
ns V_CC = 4.5V and 5.5V, C_L = 50pF
-
80
-
80
ns V_CC = 4.5V and 5.5V, C_L = 50pF
0
110
0
110
ns V_CC = 4.5V and 5.5V, C_L = 50pF
0
110
0
110
ns V_CC = 4.5V and 5.5V, C_L = 50pF
0
110
0
110
ns V_CC = 4.5V and 5.5V, C_L = 50pF
-
75
-
75
ns V_CC = 4.5V and 5.5V, C_L = 50pF
TD13 Sync Data Setup
75
-
75
-
ns V_CC = 4.5V and 5.5V, C_L = 50pF
NOTES:
1. TDC = Decoder clock period = 1/FDC.
2. AC Testing as follows: Input levels: V_IH = 70% V_CC, V_IL = 20% V_CC; Input rise/fall times driven at 1ns/V; Timing Reference
levels: V_CC/2; Output load: C_L = 50pF.
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