DG401 Datasheet, PDF (6/9 Pages) Intersil Corporation – Monolithic CMOS Analog Switches

DG401, DG403, DG405
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C₁
or C₂. Another one selects e_IN or discharges the capacitor in
preparation for the next integration cycle.
+5V
+15V
V_L
V+
e_IN
S₁
D₁
S₃
D₂
INTEGRATE/
RESET
TTL
SCOPE
SELECT
IN₁
S₂
D₃
C₁
S₄
D₄
IN₂
C₂
DG403
GND
V-
-15V
e_OUT
Peak Detector
A₃ acting as a comparator provides the logic drive for
operating SW₁. The output of A₂ is fed back to A₃ and
compared to the analog input e_IN. If e_IN > e_OUT the output
of A₃ is high keeping SW₁ closed. This allows C₁ to charge
up to the analog input voltage. When e_IN goes below e_OUT,
A₃ goes negative, turning SW₁ off. The system will therefore
store the most positive analog input experienced.
RESET
+- ^A1
e_IN
+
-
A₃
SW₂
SW₁
R₁
C₁
DG401
A_{2 eOUT}
+
-
FIGURE 8. DUAL SLOPE INTEGRATOR
FIGURE 9. POSITIVE PEAK DETECTOR
Typical Performance Curves
10
V+ = 15V
V- = -15V
8
T_A = 20^oC
6
DG403
4
SW3, 4
2
0
0 2 4 6 8 10 12 14 16 18 20
V_L (V)
FIGURE 10. INPUT SWITCHING THRESHOLD vs LOGIC
SUPPLY VOLTAGE
4
V_L
T_A
=
=
5V
25^oC
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (±V)
FIGURE 11. INPUT SWITCHING THRESHOLD vs
POWER SUPPLY VOLTAGE
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