X4163 Datasheet, PDF (5/21 Pages) Intersil Corporation – CPU Supervisor with 16K EEPROM

Figure 4. V_TRIP Programming Sequence
X4163, X4165
New V_CC Applied =
Old V_CC Applied + Error
V_TRIP Programming
Execute
Reset V_TRIP
Sequence
Set V_CC = V_CC Applied =
Desired V_TRIP
Execute
Set V_TRIP
Sequence
Apply 5V to V_CC
Decrement V_CC
(V_CC = V_CC - 50mV)
New V_CC Applied =
Old V_CC Applied - Error
Execute
Reset V_TRIP
Sequence
NO
RESET pin
goes active?
YES
Error ≤ –Emax
Emax = Maximum Allowed V_TRIP Error
Measured V_TRIP -
Desired V_TRIP
Error ≥ Emax
–Emax < Error < Emax
DONE
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, and WD0. The X4163/5 will not acknowledge
any data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4163/5 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
7
6 5 43
2
10
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
5
FN8120.0
April 13, 2005