X4163 Datasheet, PDF (13/21 Pages) Intersil Corporation – CPU Supervisor with 16K EEPROM

X4163, X4165
Figure 15. X4163/5 Addressing
Device Identifier
Device Select
1
0
1
0
0
S1
S0 R/W
Slave Address Byte
High Order Word Address
0
0
0
0
0
A10 A9
A8
(X4) (X3) (X2)
Word Address Byte 0–16K
Low Order Word Address
A7
A6 A5
A4
A3 A2
A1
A0
(X1) (X0) (Y5) (Y4) (Y3) (Y2) (Y1) (Y0)
Word Address Byte 0 for all options
D7
D6
D5
D4 D3
D2
D1
D0
Data Byte for all options
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress com-
munication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
13
FN8120.0
April 13, 2005