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| X4163 Datasheet, PDF (15/21 Pages) Intersil Corporation – CPU Supervisor with 16K EEPROM | |||
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X4163, X4165
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Symbol
COUT(4)
CIN(4)
Parameter
Output Capacitance (SDA, RST/RST)
Input Capacitance (SCL, WP)
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
SDA
or
RESET
5V
1533â¦
For VOL= 0.4V
and IOL = 3 mA
100pF
Max.
8
6
Unit
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1VCC to 0.9VCC
10ns
0.5VCC
Standard output load
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR
tF
tSU:WP
tHD:WP
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 + .1Cb
20 + .1Cb
0.6
0
Max.
400
0.9
300
300
400
Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
15
FN8120.0
April 13, 2005
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