ISL62391_11 Datasheet, PDF (5/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller

ISL62391, ISL62392, ISL62391C, ISL62392C
Functional Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Bottom
Pad
NAME
FUNCTION
PGOOD Open-drain power-good status outputs. Connect to VCC through a 100k resistor. Output will be high when all outputs are
within regulation with no faults detected.
FSET2 Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
FCCM Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full
discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.
VCC Analog power supply input for reference voltages and currents. Bypass to ground with a 1µF ceramic capacitor near the IC.
LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
FSET1 Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
FB1 SMPS1 feedback input used for output voltage programming and regulation.
VOUT1 SMPS1 output voltage sense input. Used for soft-discharge.
ISEN1 SMPS1 DCR current sense input. Used for overcurrent protection and R³ regulation.
OCSET1 Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS1.
EN1 Logic input to enable and disable SMPS1. A logic high will immediately enable SMPS1. Floating this pin will enable
SMPS1 only after SMPS2 has been enabled and achieved regulation. A logic low disables SMPS1.
PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS1.
UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
BOOT1 SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to SMPS1 PHASE with a ceramic capacitor of 0.22µF.
LGATE1 Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
LDO3 3.3V linear regulator output, capable of providing 100mA continuous current. Bypass to ground with a 4.7µF ceramic capacitor.
VIN Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
PVCC 5V power source for SMPS gate drive current. Bypass to ground with a 4.7µF ceramic capacitor.
PGND Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
LGATE2 Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
BOOT2 SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to SMPS2 PHASE with a ceramic capacitor of 0.22µF.
UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS2.
EN2 Logic input to enable and disable SMPS2. A logic high will immediately enable SMPS2. Floating this pin will enable
SMPS2 only after SMPS1 has been enabled and achieved regulation. A logic low disables SMPS2.
OCSET2 Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS2.
ISEN2 SMPS2 DCR current sense input. Used for overcurrent protection and R³ regulation.
VOUT2 SMPS2 output voltage sense input. Used for soft-discharge and switchover for PVCC 5V LDO.
FB2 SMPS2 feedback input used for output voltage programming and regulation.
GND Analog ground for analog and logic signals.
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FN6666.5
April 7, 2011