ISL62391_11 Datasheet, PDF (17/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller

ISL62391, ISL62392, ISL62391C, ISL62392C
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered in this scenario.
A capacitor dissipates heat as a function of RMS current and
frequency. Be sure that I_P-P is shared by a sufficient quantity
of paralleled capacitors so that they operate below the
maximum rated RMS current at f_SW. Take into account that
the rated value of a capacitor can fade as much as 50% as
the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input RMS ripple
current (normalized relative to output load current) as a
function of duty cycle and is adjusted for a converter efficiency
of 80%. The ripple current calculation is written as
Equation 21:
I_{IN_RMS, NORMALIZED} =
(D
–
D²)
+
⎛
⎝
D
⋅₁-^x---₂²--
⎞
⎠
(EQ. 21)
Where:
- I_MAX is the maximum continuous I_LOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I_MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as
Equation 22.
D
=
----------^V----^O------------
V_IN ⋅ EFF
(EQ. 22)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.55
0.50
0.45
0.40
0.35
0.30
x=1
0.25
x = 0.75
0.20
x = 0.50
x = 0.25
0.15
x=0
0.10
0.05
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE
FIGURE 28. NORMALIZED RMS INPUT CURRENT
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V_DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET, which has
the drain-source voltage clamped by its body diode during
turn off, the high-side MOSFET turns off with a V_DS of
approximately V_IN - V_OUT, plus the spike across it. The
preferred low-side MOSFET emphasizes low r _DS(ON) when
fully saturated to minimize conduction loss. It should be
noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For
higher output, low input voltage solutions, a more balanced
MOSFET selection for high- and low-side devices may be
warranted.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 23:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} • (1 – D)
(EQ. 23)
For the high-side (HS) MOSFET, the conduction loss is
written as Equation 24:
P_{CON_HS}
=
I_L
O
A
2
D
•
r_D
S
(
O
N
)
_
H
S
•
D
(EQ. 24)
For the high-side MOSFET, the switching loss is written as
Equation 25:
P_{SW_HS}
=
V_{-----I--N----}•_---I_{--V----A----L---L---E----Y-----}•_--t_{--O-----N----}•_---f_--S----W---
2
+
-^V----^I--^N----^•---^I--^P----^E----^A----^K----^•---^t--^O----^F----^F----^•---^f-^S----^W----
2
(EQ. 25)
17
FN6666.5
April 7, 2011