ISL62391_11 Datasheet, PDF (12/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller

ISL62391, ISL62392, ISL62391C, ISL62392C
Theory of Operation
Three Output Controller
The ISL62391, ISL62392, ISL62391C and ISL62392C
generate three regulated output voltages. Two are produced
with switch-mode power supplies (SMPS), and the third by a
low dropout linear regulator (LDO). An additional 5V LDO
(PVCC) is used to power the chip during operation, allowing
the ISL62391, ISL62392, ISL62391C and ISL62392C to
regulate all outputs from a single power source (VIN) with no
need for a separate quiescent supply. This makes the
ISL62391, ISL62392, ISL62391C and ISL62392C an ideal
choice as system regulator for notebook PCs. Because the
two SMPS channels are identical and almost entirely
independent, all conclusions drawn apply to both channels
unless otherwise noted.
Modulator and Switching Frequency
The ISL62391, ISL62392, ISL62391C and ISL62392C
modulator feature Intersil’s R³ technology, a hybrid of fixed
frequency PWM and variable frequency hysteretic control.
Intersil’s R³ technology can simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients. The R³ modulator
synthesizes an AC signal, V_R, which is an analog
representation of the output inductor ripple current. The
duty-cycle of V_R is the result of charge and discharge
current through a ripple capacitor, C_R. The current through
C_R is provided by a transconductance amplifier that
measures the VIN and VO pin voltages. The positive slope
of V_R can be written as Equation 1:
V_RPOS = g_m ⋅ (V_IN – V_OUT)
(EQ. 1)
The negative slope of V_R can be written as Equation 2:
V_RNEG = g_m ⋅ V_OUT
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
RIPPLE CAPACITOR VOLTAGE C_R
WINDOW VOLTAGE V_W
(WRT V_COMP)
ERROR AMPLIFIER
VOLTAGE V_COMP
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is set by a resistor, R_W, connected across the FSET and
GND pins. The V_R, V_COMP, and V_W signals feed into a
window comparator in which V_COMP is the lower threshold
voltage and V_W is the higher threshold voltage. Figure 23
shows PWM pulses being generated as V_R traverses the
V_W and V_COMP thresholds. The PWM switching frequency
is proportional to the slew rates of the positive and negative
slopes of V_R; it is inversely proportional to the voltage
between V_W and V_COMP. Equation 3 illustrates how to
calculate the window size based on output voltage and
frequency set resistor.
V_W = g_m ⋅ V_OUT ⋅ (1 – D) ⋅ R_W
(EQ. 3)
The frequency can be expressed in Equation 4:
F_SW
=
--------¹---------
K ⋅ R_W
(EQ. 4)
Inverting Equation 4 allows easy selection of R_W for a
desired F_SW:
R_W = -_K-----_â‹---_F1----_S----_W---
(EQ. 5)
For Equations 3 through 5:
g_m = 1.66µs
K = 1.7 x 10^-10 (±20%)
D = V_OUT/V_IN
Power-On Reset
The ISL62391, ISL62392, ISL62391C and ISL62392C are
disabled until the voltage at the VIN pin has increased above
the rising power-on reset (POR) threshold. Conversely, the
controller will be disabled when the voltage at the VIN pin
decreases below the falling POR threshold.
In addition to VIN POR, the PVCC pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
The ISL62391, ISL62392, ISL62391C and ISL62392C use a
digital soft-start circuit to ramp the output voltage of each
SMPS to the programmed regulation setpoint at a
predictable slew rate. The slew rate of the soft-start
sequence has been selected to limit the in-rush current
through the output capacitors as they charge to the desired
regulation voltage. When the EN pins are pulled above their
rising thresholds, the PGOOD Soft-Start Delay, t_SS, starts and
the output voltage begins to rise. The FB pin ramps to 0.6V in
approximately 1.5ms and the PGOOD pin goes to high
impedance approximately 1.25ms after the FB pin voltage
reaches 0.6V.
12
FN6666.5
April 7, 2011