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ISL6161 Datasheet, PDF (5/11 Pages) Intersil Corporation – Dual Power Distribution Controller
ISL6161
Electrical Specifications
VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = -40°C to
+85°C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
±1% Current Limit Response Time
(Current within 1% of Regulated Value)
200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-
10
-
µs
Response Time To Dead Short
RTSHORT CVG = 0.01µF
-
500
ns
Gate Turn-On Time
tON3V CVG = 0.01µF
-
5
-
ms
Gate Turn-On Current
ION3V CVG = 0.01µF
8
10
12
µA
3x Gate Discharge Current
3xdisI CVG = 0.01µF, ENABLE = Low
0.75
-
A
3.3V Undervoltage Threshold
3.3VVUV
2.7
2.85
3.0
V
3.3VG High Voltage
3VG
11.2
11.9
-
V
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current
VDD POR Rising Threshold
VDD POR Falling Threshold
Current Limit Time-Out
ENABLE Pull-up Voltage
IVDD
tILIM
CTIM = 0.1µF
PWRN_V ENABLE pin open
4
8
10
mA
9.5
10.0
10.7
V
9.0
9.4
9.8
V
-
20
-
ms
1.8
2.4
3.2
V
ENABLE Rising Threshold
PWR_Vth
1.1
1.5
2
V
ENABLE Hysteresis
PWR_hys
0.1
0.2
0.3
V
ENABLE Pull-Up Current
PWRN_I
60
80
100
µA
Current Limit Time-Out Threshold (CTIM)
CTIM Charging Current
CTIM Discharge Current
CTIM Pull-Up Current
RILIM Pin Current Source Output
Charge Pump Output Current
Charge Pump Output Voltage
CTIM_Vth
CTIM_I
CTIM_disI
CTIM_disI
RILIM_Io
Qpmp_Io
Qpmp_Vo
VCTIM = 8V
CPUMP = 0.1µF, CPUMP = 16V
No load
1.8
2
2.2
V
8
10
12
µA
1.7
2.6
3.5
mA
3.5
5
6.5
mA
90
100
110
µA
320
560
900
µA
17.2
17.4
-
V
Charge Pump Output Voltage - Loaded
Qpmp_VIo Load current = 100µA
16.2
16.7
-
V
Charge Pump POR Rising Threshold
Qpmp + Vth
15.6
16
16.5
V
Charge Pump POR Falling Threshold
Qpmp - Vth
15.2
15.7
16.2
V
ISL6161 Description and Operation
The ISL6161 is a multi-featured +12V and +3.3V dual power
supply distribution controller. Its features include programmable
current regulation (CR) limiting and time to latch off.
At turn-on, the gate capacitor of each external N-Channel
MOSFET is charged with a 10µA current source. These
capacitors create a programmable ramp (soft turn-on). A
charge pump supplies the gate drive for the 12V supply control
FET switch driving that gate to 17V.
The load currents pass through two external current sense
resistors. When the voltage across either resistor quickly
exceeds the user programmed Current Regulation voltage
threshold (CRVth) level, the controller enters current regulation.
The CRVth is set by the external resistor value on RILIM pin. At
this time, the time-out capacitor, CTIM, starts charging with a
10µA current source and the controller enters the time-out
period. The length of the time-out period is set by the single
external capacitor (see Table 2) placed from the CTIM pin
(pin 10) to ground and is characterized by a lowered gate drive
voltage to the appropriate external N-Channel MOSFET. Once
CTIM charges to 2V, an internal comparator is tripped resulting
in both N-Channel MOSFETs being latched off. If the voltage
across the sense resistors rises slowly in response to an OC
condition, then the CR mode is entered at ~95% of the
programmed CR level. This difference is due to the necessary
hysteresis and response time in the CR control circuitry.
Table 1 shows RSENSE and RILIM recommendations and
resulting CR level for the PCI-Express add-in card connector
sizes specified.
5
FN9104.4
October 2, 2008