ISL59911_14 Datasheet, PDF (5/17 Pages) Intersil Corporation – 250MHz Triple Differential Receiver/ Equalizer with I2C Interface

ISL59911
Electrical Specifications V+ = V+_R = V+_G = V+_B = +5V, V- = V-_R = V-_G = V-_B = V-_D = -5V, T_A = +25°C, all registers at default settings
(equalizer stages set to minimum boost, noise filter set to max bandwidth, x2 gain mode, GAIN_DC = 0dB), all analog inputs at 0V, auto offset
calibration executed, R_L = 5pF || (75Ω + 75Ω) to GND, thermal pad connected to -5V, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNIT
BW_CM
Common Mode Amplifier Bandwidth
SR_CM
Common Mode Slew Rate
INPUT CHARACTERISTICS
10k || 5pF load
V_IN = -0.5V to +1.5V
24
MHz
0.1
V/ns
CMIR
Common-mode Input Range
Differential signal passed undistorted.
-3.2/+4.0
V
Effective headroom is reduced by the p-p
amplitude of differential swing divided by 2.
CMRR
Common-mode Rejection Ratio
Measured at 100kHz
88
dB
Measured at 10MHz
58
dB
C_INDIFF
R_INDIFF
Differential Input Capacitance
Differential Input Resistance
Capacitance between V_INP and V_INM
Resistance between V_IN+ and V_IN-
(due to common mode input resistance)
0.5
pF
20
kΩ
C_INCM
CM Input Capacitance
Capacitance from V_IN+ and V_IN- to GND
1.3
pF
R_INCM
CM Input Resistance
Resistance from V_IN+ and V_IN- to GND
25
kΩ
V_{INDIFF_P-P}
Max P-P Differential Input Range
Delta V_IN+ - V_IN- when slope gain falls to 0.9
1.9
V
OUTPUT CHARACTERISTICS
V_OUT
I_OUT
V(V_OUT)_OS
R(V_CM)
Output Voltage Swing
Output Drive Current
Output Offset Voltage
R_L = 10Ω, V_IN+ - V_IN- = ±2V
Post-offset calibration
CM Output Resistance of VCM_R/G/B At 100kHz
(CM Output Mode)
±2.75
V
±22
mA
-20
-8
+5
mV
2.5
Ω
Gain
Gain
x1 mode
x2 mode
0.95
1.0
1.05 V/V
1.9
2.0
2.1
ΔGain
Channel-to-Channel Gain Mismatch x1 and x2 modes
±3
%
O_NOISE
Integrated Noise at Output
Inputs @ GND through 50Ω.
0m of Equalization (Nominal)
300m of Equalization
4
mV_RMS
20
SYNCOUT_HI
SYNCOUT_LO
SCL, SDA PINS
f_MAX
V_OL
V_IH
V_IL
V_HYST
I_LEAKAGE
t_GLITCH
High Level output on VS/HS_OUT
Low Level output on VS/HS_OUT
10k || 5pF load, SYNC Output Mode
10k || 5pF load, SYNC Output Mode
Maximum I²C Operating Frequency
SDA Output Low Level
Input High Level
Input Low Level
Input Hysteresis
Input Leakage Current
Maximum Width of Glitch on SCL (or
SDA) Guaranteed to be Rejected
V_SINK = 6mA
V+ - 1.5
V
0.4
V
400
kHz
0.4
V
3
V
1.5
V
0.55
V
±1
µA
50
ns
ENABLE, ADDR0, ADDR1 PINS
V_IH
Input High Level
3
V_IL
Input Low Level
I_LEAKAGE
Input Leakage Current
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
V
0.8
V
±1
µA
5
FN7548.0
September 2, 2011