ISL59911_14 Datasheet, PDF (14/17 Pages) Intersil Corporation – 250MHz Triple Differential Receiver/ Equalizer with I2C Interface

ISL59911
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
Configuration Register Write
Figure 17 shows two views of the steps necessary to write one or
more words to the Configuration Register.
START Command
ISL59911 Serial Bus
R/W
1
0
0
0
1 ADDR1 ADDR0 0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
(Repeat if desired)
Signals the beginning of serial I/O
ISL59911 Device Select Address Write
The first 7 bits of the first byte select the ISL59911 on the 2-wire
bus at the address set by the ADDR0 and ADDR1 pins. The
R/W bit is a 0, indicating that the next transaction will be a write.
ISL59911 Register Address Write
This is the address of the ISL59911’s Configuration Register
that the following byte will be written to.
ISL59911 Register Data Write(s)
This is the data to be written to the ISL59911’s Configuration
Register. Note: The ISL59911 Configuration Register’s address
pointer auto-increments after each data write. Repeat this step to
write multiple sequential bytes of data to the Configuration Register.
Signals from
the Host
SDA Bus
Signals from
the ISL59911
STOP Command
Signals the ending of serial I/O
S
T _{Serial Bus}
A
R
Address
T
Register
Address
Data
Write*
S
T
* The Data Write step can be repeated to write to the
O ISL59911’s Configuration Register sequentially, beginning at
P _{the Register Address written in the previous step.}
a a a a a a a 0 AAAAAAAA d d d d d d d d
A
A
A
C
C
C
K
K
K
FIGURE 17. CONFIGURATION REGISTER WRITE
14
FN7548.0
September 2, 2011