ISL59911_14 Datasheet, PDF(11/17 Page) Intersil Corporation – 250MHz Triple Differential Receiver/ Equalizer with I2C Interface

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ISL59911_14 Datasheet, PDF (11/17 Pages) Intersil Corporation – 250MHz Triple Differential Receiver/ Equalizer with I2C Interface

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ISL59911

Length

(m)

100

125

150

175

200

225

250

275

300

TABLE 1. Cat 5 LOOK-UP TABLE

Reg

0x00

0x20

0x11

0x10

0x00

0x24

0x22

0x21

0x01

0x25

0x33

0x31

0x01

0x49

0x44

0x42

0x01

0x69

0x55

0x53

0x02

0x89

0x75

0x62

0x02

0x92

0x86

0x72

0x04

0x96

0x82

0x06

0x97

0xA7

0x93

0x08

0xB7

0xB8

0xB2

0x09

0xD7

0xC9

0xC3

0x0A

0xF7

0xEA

0xD2

0x0C

Reg

6-8

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

Offset Calibration

Historically, programmable video equalizer ICs have had large

and varying offset voltages, often requiring external circuitry

and/or manual trim to reduce the offset to acceptable levels. The

ISL59911 improves upon this by adding an offset calibration

circuit that, when triggered by setting bit 0 of I2C register 0x0C,

shorts the inputs together internally, compares the ROUT, GOUT,

and BOUT voltages to their corresponding RREF, GREF, and BREF

voltages and uses a DAC with a successive-approximation

technique to minimize the delta between them (see Figure 12).

VIN+

VIN-

INPUT

BUFFER

EQ AND

GAIN

DAC

OUTPUT

BUFFER

VOUT

SAR

LOGIC

COMPARATOR

VREF

FIGURE 12. OFFSET CALIBRATION (ONE CHANNEL SHOWN)

When the ISL59911 is first powered up, the offset error is

undefined until an offset calibration is performed. The output

offset voltage of the ISL59911 also varies as the filter and gain

settings are adjusted. To minimize offset, always perform an

offset calibration after finalizing the filter and gain settings.

An offset calibration only takes about 3Î¼s, so offset calibrations

can be performed after every register write without adding

significant time to the adjustment process. This minimizes offset

throughout the entire equalization adjustment procedure.

Output Signals

The ROUT, GOUT, and BOUT outputs can drive either a standard

75Î© video load in x1 gain mode or a 150Î© source-terminated

load (75Î© in series at source end [ISL59911 output pin], plus

75Î© termination to ground at receive end) in x2 mode. If the

output of the ISL59911 is going directly into an ISL59920 or

similar delay line, termination to ground is not necessary,

however, a ~75Î© series resistor at each output pin will help

isolate the outputs from the PCB trace capacitance, improving

the flatness of the frequency response.

When ENABLE is low, the ROUT, GOUT, and BOUT outputs are put

in a high-impedance state, allowing multiple ISL59911 devices

to be configured as a multiplexer by paralleling their outputs and

using ENABLE to select the active RGB channel.

Common Mode and HSYNC/VSYNC Outputs

In addition to the incoming differential video signals, the

ISL59911 also processes the common mode voltage on the

differential inputs and can output the signal in one of two ways

(as determined by the Output Configuration bit in register 0x01).

When the Output Configuration bit is set to 0 (the default), the

common mode input voltages are sent to comparators that

decode the voltage into HSYNC and VSYNC signals according to

the EL4543/ISL59311 standard encoding scheme shown in

Figure 13 and in Table 2 on page 11. The HSYNC signal appears

on the HSOUT/RCM pin, the VSYNC signal on VSOUT/GCM. The BCM

output pin is held at a logic low (0v).

To minimize noise coupling into the analog section from the sync

output drivers, the HSOUT and VSOUT outputs have limited current

drive, and should be buffered by 74HC04 or similar CMOS

buffers, as shown in Figure 1, before driving any significant loads

(such as a VGA cable).

When the Output Configuration bit is set to 1, buffered versions

of the three common mode input voltages are available on the

RCM, GCM, and BCM pins. Making the raw common mode signal

available allows for custom encoding schemes and/or

transmission of analog signals on the video signalsâ common

mode.

3.0V

2.0V

3.0V

2.0V

3.0V

2.0V

2.5V

BLUE CM

GREEN CM

RED CM

VSYNC

HSYNC

TIME (0.5ms/DIV)

FIGURE 13. H AND V SYNC SIGNAL ENCODING

RED CM

2.5V

3.0V

2.0V

2.5V

TABLE 2. H AND V SYNC DECODING

GREEN CM

3.0V

BLUE CM

2.0V

HSYNC

Low

2.0V

2.5V

Low

3.0V

2.5V

High

2.0V

3.0V

High

VSYNC

Low

High

Low

High

FN7548.0

September 2, 2011

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