ISL54105A_14 Datasheet, PDF (5/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105A
Pin Descriptions
SYMBOL
DESCRIPTION
RX0-, RX0+, RX1-, RX1+, RX2-, RX2+ TMDS Inputs. Incoming TMDS data signals.
RXC-, RXC+
TMDS Inputs. Incoming TMDS clock signals.
TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TMDS Outputs. TMDS output data for selected channel.
TXC-, TXC+
TMDS Outputs. TMDS output clock for selected channel.
SCL
SDA
ADDR[6:0]
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Note: Internal 65kΩ pull-up to V_D.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
Note: Internal 65kΩ pull-up to V_D.
Digital inputs, 5V tolerant. 7-Bit address for serial interface.
Note: Internal 60kΩ pull-down to GND.
AD
Digital Output, 3.3V. AD = Activity Detect. Output goes high when an active TMDS clock is detected on
RXC.
RES_BIAS
Tie to GND through a 3.16k external resistor. Sets up internal bias currents.
RES_TERM
Tie to VD through a 1.0k 1% external resistor. During calibration, the termination resistor closest in value
to RES_TERM/20 (= 50Ω) is selected.
PD
Digital Input, 3.3V. PD = Power-down. Pull high to put the ISL54105A in a minimum power consumption
mode.
Note: To ensure proper operation, this pin must be held low during power-up. It may be taken high 100ms
after the power supplies have settled to 3.3V ±10%.
When exiting Power-down, a termination resistor Recalibration cycle must be run to re-trim the
termination resistors (see register 0x03[7]).
Note: Internal 60kΩ pull-down to GND.
RESET
Digital Input, 3.3V. Pull high then low to reset the mux. Tie to GND in final application.
Note: Internal 60kΩ pull-down to GND.
TEST
Digital Input. Used for production testing only. Tie to GND in final application. This pin has an internal
pulldown to GND, so it is also acceptable to leave this pin floating.
V_D
V_D_ESD
THERMAL PAD (GND)
Power supply. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
Power supply for ESD protection diodes. Connect one of these pins (pin 41 or 53) to the 3.3V V_D supply
rail with a low V_F (0.4V or lower) Schottky diode, with the cathode connected to V_D_ESD and the anode
connected to V_D. Bypass each pin to GND with 0.1µF.
Ground return for the entire chip. The thermal pad must have a low impedance connection to GND for
the ISL54105A to function at all. The lower electrical impedance, the better the ground, and the better the
performance. A low thermal impedance between the thermal pad and the GND plane of the PCB will
dissipate the heat from the package more efficiently as well and is recommended.
5
FN6716.0
June 4, 2008