ISL54105A_14 Datasheet, PDF (12/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105A
PCB Layout Recommendations
Because of the high speed of the TMDS signals, careful
PCB layout is critical to maximize performance. The
following guidelines should be adhered to as closely as
possible:
• All TMDS pair traces should have a characteristic
impedance of 50Ω with respect to the power/ground
planes and 100Ω with respect to each other. Failure to
meet this requirement will increase reflections, shrinking
the available eye.
• Avoid vias for all 3 high speed TMDS pairs. Vias add
inductance which causes a discontinuity in the
characteristic impedance of the trace. Keep all the traces
on the top (or the bottom) of the PCB. The TMDS clock
can have vias if necessary, since it is lower speed and less
critical. If you must use a via, ensure the vias are
symmetrical (put identical vias in both lines of the
differential pair).
• For each TMDS channel, the trace lengths of the 3 TMDS
pairs (0, 1 and 2) should ideally be the same to reduce
inter channel skew introduced by the board.
• The trace length of the clock pair is not critical at all.
Since the clock is only used as a frequency reference, its
phase/delay is inconsequential. In addition, since the
TMDS clock frequency is 1/10th the pixel rate, the clock
signal itself is much more noise-immune. So liberties
(such as vias and circuitous paths) can be taken when
routing the clock lines.
• Minimize capacitance on all TMDS lines. The lower the
capacitance, the sharper the rise and fall times.
• Maintain a constant, solid ground (or power) plane under
the 3 high speed TMDS signals. Do not route the signals
over gaps in the ground plane or over other traces.
• Ideally each supply should be bypassed to ground with a
0.1µF capacitor. Minimize trace length and vias to
minimize inductance and maximize noise rejection.
Figure 12 demonstrates a common but non-ideal PCB
layout and its equivalent circuit. The additional trace
resistance between the bypass capacitor and the power
supply/IC reduces its effectiveness. Figure 13
demonstrates a better layout. In this case there is still
series trace resistance (it is impossible to completely
eliminate it), but now it is being put to good use, as part of
a “T” filter, attenuating supply noise before it gets to the IC,
and reducing the amount of IC-generated noise that gets
injected into the supply. Follow the good supply bypassing
rules shown in Figure 13 to the extent possible.
VIA TO
POWER
PLANE
CBYPASS
V⁺
IC
VIAS
TO
GND
GND
EQUIVALENT CIRCUIT
POWER PLANE
RVIA
RTRACE
RTRACE
V⁺
V⁺
CBYPASS
IC
GND
GROUND PLANE
FIGURE 12. SUB-OPTIMAL BYPASS CAPACITOR LAYOUT
VIA TO
POWER
PLANE
V⁺
CBYPASS
IC
GND
VIAS
TO
GND
EQUIVALENT CIRCUIT
POWER PLANE
RVIA
RTRACE
RTRACE
V⁺
V⁺
CBYPASS
IC
GND
GROUND PLANE
FIGURE 13. OPTIMAL (“T”) BYPASS CAPACITOR LAYOUT
12
FN6716.0
June 4, 2008