ISL54105A_14 Datasheet, PDF (11/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105A
drawing current from the external TMDS receiver it is
attached to.
3.3V_TX
V_D
3.3V_RX
Rx_N
50
V_D_ESD ^{(41, 53)}
Tx
Tx_N
discontinuity. This adds up to 2 bits of skew in addition to any
incoming skew, as shown in the following examples.
Figure 10 shows an input (the top three signals) with
essentially no skew. After the ISL54105A locks on to the
signal, there may be 1 bit of skew on the output, as shown in
Figure 10.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
INPUT SKEW
(none, in this Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
example)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
ISL54105A
FIGURE 8. ISL54105A ESD PROTECTION DIODES
This is non-ideal and can cause the ISL54105A to fail HDMI
Compliance Test 7-3 (“V_OFF”). V_OFF is the voltage across
each 50Ω Rx_N resistor when the power is removed from the
device containing the ISL54105A.
To prevent this leakage current, insert a Schottky diode
between the V_D power net and the V_D_ESD pins as shown
in Figure 9. With the addition of this diode the system will
pass compliance test 7-3.
3.3V_TX
V_D
D₁
V_D_ESD
C₁
0.1μF
(41, 53)
Tx
3.3V_RX
Rx_N
50
Tx_N
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 B
OUTPUT SKEW
(1 bit – 615ps at Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
162.5Mpixels/s)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
FIGURE 10. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
FOR INPUTS WITH NO OR LITTLE SKEW
When there is pre-existing skew on the input, the ISL54105A
can add up to 2 bits to the channel-to-channel skew. In the
example in Figure 11, the incoming red channel has 2.3 bits
of skew relative to the incoming green and blue. The FIFO’s
quantization (worst case) increases the total skew to 4.0 bits.
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5
INPUT SKEW
(2.3 bits/1.4ns Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7
in this example)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7
ISL54105A
FIGURE 9. SCHOTTKY DIODE MODIFICATION
Inter-Pair (Channel-to-Channel) Skew
The read pointers for Channel 0, 1, and 2 of the FIFO that
follows the CDR all have the same clock, so all 3 channels
transition within a few picoseconds of each other - there is
essentially no skew between the transitions of the three
channels.
However the FIFO read pointers may be positioned up to 2
bits apart relative to each other, introducing a random, fixed
channel-to-channel skew of skew of 1 or (much less
frequently) 2 bits. The random skew is introduced whenever
there is a discontinuity in the input signal (typically a video
mode change or a new mux channel selection). After the
CDRs and PLL lock, the skew is fixed until the next
11
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
OUTPUT SKEW
(4 bits/2.5ns at Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7
162.5Mpixels/s)
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8
FIGURE 11. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
FOR INPUTS WITH MODERATE TO LARGE
SKEW
While increasing skew is not desirable, DVI and HDMI
receivers are required to have a minimum of 6 bits of inter-
pair skew tolerance, so the addition of 2 bits of skew is only a
problem with the most pathological cables and transmitters.
It does, however, limit the number of ISL54105As that can
be put in series (although statistically it is unlikely that all the
skews would line up in a worst-case configuration).
FN6716.0
June 4, 2008