ISL54105A_14 Datasheet, PDF (14/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105A
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
START Command
Signals the beginning of serial I/O
ISL54105A Serial Bus
R/W
ISL54105A Device Select Address Write
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0
The first 7 bits of the first byte select the ISL54105A on the 2-
wire bus at the address set by the ADDR[6:0} pins. The R/W bit
is a 0, indicating that the next transaction will be a write.
ISL54105A Register Address Write
A7
A6
A5
A4
A3
A2
A1
A0 _{This is the address of the ISL54105A’s configuration register}
that the following byte will be written to.
ISL54105A Register Data Write(s)
D7
D6
D5
D4
D3
D2
D1
D0 _{This is the data to be written to the ISL54105A’s configuration}
(Repeat if desired)
register.
Note: The ISL54105A’s Configuration Register’s address pointer
auto increments after each data write: repeat this step to write
multiple sequential bytes of data to the Configuration Register.
STOP Command
Signals the ending of serial I/O
Signals from
the Host
S
T _{Serial Bus}
A
R
Address
T
Register
Address
Data
Write*
S
T
* The data write step may be repeated to write to the
O ISL54105A’s Configuration Register sequentially, beginning at
P _{the Register Address written in the previous step.}
SDA Bus
Signals from
the
a a a a a a a 0 AAAAAAAA d d d d d d d d
A
A
A
C
C
C
K
K
K
FIGURE 17. CONFIGURATION REGISTER WRITE
14
FN6716.0
June 4, 2008