ISL43231_06 Datasheet, PDF (5/15 Pages) Intersil Corporation – Low-Voltage, Single and Dual Supply, Triple SPDT Analog Switch

ISL43231
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, V_INH = 4V, V_INL = 0.8V (Note 3),
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP (NOTE 4)
(°C)
MIN
(NOTE 4)
TYP
MAX UNITS
ON Resistance, R_ON
V+ = 10.8V, I_COM = 1.0mA, V_NO or V_NC = 9V
(See Figure 6)
25
-
Full
-
37
45
Ω
-
55
Ω
R_ON Matching Between Channels, V+ = 10.8V, I_COM = 1.0mA, V_NO or V_NC = 9V (Note 5) 25
-
1.2
2
Ω
∆R_ON
Full
-
-
2
Ω
R_ON Flatness, R_FLAT(ON)
V+ = 10.8V, I_COM = 1.0mA, V_NO or V_NC = 3V, 6V, 9V
25
-
5
7
Ω
(Note 6)
Full
-
-
7
Ω
NO or NC OFF Leakage Current, V+ = 13.2V, V_COM = 1V, 12V, V_NO or V_NC = 12V, 1V
25
-0.1
0.002
0.1
nA
I_NO(OFF) or I_NC(OFF)
(Note 7)
Full
-2.5
-
2.5
nA
COM OFF Leakage Current,
I_COM(OFF)
V+ = 13.2V, V_COM = 12V, 1V, V_NO or V_NC = 1V, 12V
25
-0.1
0.002
0.1
nA
(Note 7)
Full
-2.5
-
2.5
nA
COM ON Leakage Current,
I_COM(ON)
V+ = 13.2V, V_COM = 1V, 12V, V_NO or V_NC = 1V, 12V,
25
-0.1
0.002
0.1
nA
or floating (Note 7)
Full
-2.5
-
2.5
nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V_INH, V_ADDH
Input Voltage Low, V_INL, V_ADDL
Input Current, I_ADDH, I_ADDL, I_ENH, V+ = 13.2V, V_INH, V_ADD = 0V or V+
I_ENL
Input Current, I_ENH, I_LEH
V+ = 13.2V, V_INH, V_ADD = 0V or V+
Input Current, I_ENL, I_LEL
V+ = 13.2V, V_INH, V_ADD = 0V or V+
DYNAMIC CHARACTERISTICS
Full
3.7
3.3
Full
-
2.7
Full
-0.5
-
Full
-1.5
-
Full
-4
-
-
V
0.8
V
0.5
µA
1.5
µA
4
µA
Enable Turn-ON Time, t_ON
V+ = 10.8V, V_NO or V_NC = 10V, R_L =300Ω, C_L = 35pF, 25
-
V_IN = 0 to 4 (See Figure 1)
Full
-
24
40
ns
45
ns
Enable Turn-OFF Time, t_OFF
V+ = 10.8V, V_NO or V_NC = 10V, R_L =300Ω, C_L = 35pF, 25
-
V_IN = 0 to 4 (See Figure 1)
Full
-
15
30
ns
35
ns
Address Transition Time, t_TRANS V+ = 10.8V, V_NO or V_NC = 10V, R_L =300Ω, C_L = 35pF, 25
-
V_IN = 0 to 4 (See Figure 1)
Full
-
27
50
ns
-
55
ns
Break-Before-Make Time Delay, t_D V+ = 13.2V, R_L = 300Ω, C_L = 35pF, V_NO or V_NC = 10V, Full
2
5
V_IN = 0 to 4 (See Figure 3)
Latch Setup Time, t_S
(See Figure 4)
25
25
-
Full
35
-
-
ns
-
ns
-
ns
Latch Hold Time, t_H
(See Figure 4)
25
0
-
-
ns
Full
0
-
-
ns
Latch Pulse Width, t_WPW
(See Figure 4)
25
15
-
Full
25
-
-
ns
-
ns
Charge Injection, Q
OFF Isolation
Crosstalk, Note 8
C_L = 1.0nF, V_G = 0V, R_G = 0Ω (See Figure 2)
25
-
2.7
5
pC
R_L = 50Ω, C_L = 15pF, f = 100kHz,
25
-
92
-
dB
V_NOx or V_NCx= 1V_RMS (See Figures 5, 7 and 20)
25
-
<-110
-
dB
All Hostile Crosstalk, Note 8
25
-
-105
1.5
dB
NO or NC OFF Capacitance, C_OFF f = 1MHz, V_NO or V_NC = V_COM = 0V (See Figure 8)
25
-
3
-
pF
5
FN6054.2
February 27, 2006