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ISL43231_06 Datasheet, PDF (10/15 Pages) Intersil Corporation – Low-Voltage, Single and Dual Supply, Triple SPDT Analog Switch | |||
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ISL43231
Test Circuits and Waveforms (Continued)
3V
LOGIC
INPUT
0V
tr < 20ns
tf < 20ns
SWITCH
OUTPUT
VOUT
0V
tBBM
80%
C
V+
LOGIC
INPUT
V+
C
V-
C
EN, LE
NCX, NOX
ADDX
COMX
GND EN
VOUT
RL
300â¦
CL
35pF
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 3A. tBBM MEASUREMENT POINTS
FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
tMPW
tr < 20ns
tf < 20ns
LOGIC 3V
INPUT
LE
0V
50%
tH
LOGIC 3V
INPUT
ADDX 0V
50%
tS
50%
50%
tH
50%
tON, tOFF
VNCX
SWITCH
OUTPUT
0V
VOUT
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
V-
C
C
C
LOGIC
INPUT
LOGIC
INPUT
EN
ADDX
NCX
V+
NOX
VOUT
LE GND EN COMX
RL
300â¦
CL
35pF
Repeat test for other switches. CL includes fixture and stray
capacitance.
VOUT = V(NO or NC) -R----L-----+--R--R---L--(--O-----N----)
FIGURE 4A. LATCH tS, tH, tMPW MEASUREMENT POINTS
FIGURE 4B. LATCH tS, tH, tMPW TEST CIRCUIT
FIGURE 4. LATCH SETUP AND HOLD TIMES
V+
C
V-
C
SIGNAL
GENERATOR
EN, LE
NO or NC
ANALYZER
RL
ADDX
0V or V+
COM GND
0V or V+
EN
FIGURE 5. OFF ISOLATION TEST CIRCUIT
10
V+
C
V-
C
RON = V1/1mA
VNX
EN, LE
NO or NC
1mA
V1
0V or V+
ADDX
COM
GND EN
FIGURE 6. RON TEST CIRCUIT
FN6054.2
February 27, 2006
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