ISL22426 Datasheet, PDF (5/15 Pages) Intersil Corporation – Low Noise, Low Power, SPI Bus, 128 Taps

ISL22426
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 22) (Note 5) (Note 22) UNIT
t_ShdnRec DCP Recall Time From Shutdown
From rising edge of SHDN signal to wiper
1.5
µs
(Note 21) Mode
stored position and RH connection
SCK rising edge of last bit of ACR data byte
1.5
µs
to wiper stored position and RH connection
Vpor Power-on Recall Voltage
VccRamp
t_D
V_CC Ramp Rate
Power-up Delay
Minimum V_CC at which memory recall occurs
2.0
0.2
V_CC above Vpor, to DCP Initial Value
Register recall completed, and SPI Interface
in standby state
2.6
V
V/ms
3
ms
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T ≤ +55°C
50
Years
t_WC
Non-volatile Write Cycle Time
(Note 19)
12
20
ms
SERIAL INTERFACE SPECIFICATIONS
V_IL
SHDN, SCK, SDI, and CS Input Buffer
LOW Voltage
-0.3
0.3*V_CC
V
V_IH
SHDN, SCK, SDI, and CS Input Buffer
HIGH Voltage
0.7*V_CC
V_CC + 0.3
V
Hysteresis SHDN, SCK, SDI, and CS Input Buffer
Hysteresis
0.05*V_CC
V
V_OL
SDO Output Buffer LOW Voltage
I_OL = 4mA
0
R_pu
SDO Pull-up Resistor Off-chip
(Note 20)
Maximum is determined by t_RO and t_FO with
maximum bus load Cb = 30pF, f_SCK = 5MHz
Cpin SHDN, SCK, SDI, SDO and CS Pin
(Note 21) Capacitance
0.4
V
2
kΩ
10
pF
f_SCK
t_CYC
t_WH
t_WL
t_LEAD
t_LAG
t_SU
t_H
t_RI
t_FI
t_DIS
t_V
t_HO
t_RO
SPI Frequency
SPI Clock Cycle Time
SPI Clock High Time
SPI Clock Low Time
Lead Time
Lag Time
SDI, SCK and CS Input Set-up Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO Output Disable Time
SDO Output Valid Time
SDO Output Hold Time
SDO Output Rise Time
R_pu = 2k, Cb = 30pF
5
MHz
200
ns
100
ns
100
ns
250
ns
250
ns
50
ns
50
ns
10
ns
10
20
ns
0
100
ns
350
ns
0
ns
60
ns
5
FN6180.2
September 8, 2009