ISL22426 Datasheet, PDF (11/15 Pages) Intersil Corporation – Low Noise, Low Power, SPI Bus, 128 Taps

ISL22426
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial value.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper
terminal (RW) is closest to its “Low” terminal (RL). When the
WR register of a DCP contains all ones (WR[6:0]= 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22426 is being powered up, all four WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).
The WRs can be read or written to directly using the SPI
serial interface as described in the following sections. The
SPI interface register address bits have to be set to 0000b or
0001b to access the WR of DCP0 or DCP1 respectively. The
WRi and IVRi can be read or written to directly using the SPI
serial interface as described in the following sections.
Memory Description
The ISL22426 contains seven non-volatile and three volatile
8-bit registers. The memory map of ISL22426 is shown in
Table 1. The two non-volatile registers (IVRi) at address 0
and 1, contain initial wiper value and volatile registers (WRi)
contain current wiper position. In addition, five non-volatile
General Purpose registers from address 2 to address 6 are
available.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
—
ACR
7
Reserved
TABLE 1. MEMORY MAP (Continued)
ADDRESS
NON-VOLATILE
VOLATILE
6
General Purpose
5
General Purpose
4
General Purpose
3
General Purpose
2
General Purpose
Not Available
Not Available
Not Available
Not Available
Not Available
1
IVR1
0
IVR0
WR1
WR0
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7 6 5 4
3
2
1
0
Bit Name VOL SHDN WIP 0
0
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically ANDed with SHDN pin. When this
bit is 0, DCP is in Shutdown mode. The default value of
SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write to the
IVRi, WRi or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
TABLE 3.
SHDN pin
SHDN bit
Mode
High
1
Normal operation
Low
1
Shutdown
High
0
Shutdown
Low
0
Shutdown
SPI Serial Interface
The ISL22426 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22426. SCK and CS lines are
11
FN6180.2
September 8, 2009