ISL22426 Datasheet, PDF (2/15 Pages) Intersil Corporation – Low Noise, Low Power, SPI Bus, 128 Taps

Block Diagram
SCK
SDI
SDO
CS
SPI
INTERFACE
SHDN
ISL22426
V_CC
POWER-UP
INTERFACE,
CONTROL
AND STATUS
LOGIC
NON-
VOLATILE
REGISTERS
WR1
WR0
RH1
RW1
RL1
RH0
RW0
RL0
GND
Pin Descriptions
TSSOP PIN
NUMBER
1
2
3
4
5
6
7
QFN PIN
NUMBER
15
16
1
2
3
4, 5, 9
6
SYMBOL
V_CC
SHDN
RH0
RL0
RW0
NC
SCK
Power supply pin
Shutdown active low input
“High” terminal of DCP0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
No connect
SPI interface clock input
DESCRIPTION
8
7
SDO
Open drain SPI interface Data Output
9
8
GND
Device ground pin
10
10
RW1
“Wiper” terminal of DCP1
11
11
RL1
“Low” terminal of DCP1
12
12
RH1
“High” terminal of DCP1
13
13
CS
Chip Select active low input
14
14
SDI
SPI interface Data Input
EPAD*
Exposed Die Pad internally connected to GND
*NOTE: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
2
FN6180.2
September 8, 2009