ISL22319 Datasheet, PDF (5/13 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer XDCP

ISL22319
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 14) (Note 3) (Note 14) UNIT
SERIAL INTERFACE SPECS
V_IL
A1, A0, SHDN, SDA, and SCL Input
Buffer LOW Voltage
-0.3
0.3*V_CC
V
V_IH
A1, A0, SHDN, SDA, and SCL Input
Buffer HIGH Voltage
0.7*V_CC
V_CC+0.3
V
Hysteresis SDA and SCL Input Buffer Hysteresis
V_OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
V_CC
0
V
0.4
V
Cpin
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
10
pF
f_SCL
t_sp
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
400
kHz
50
ns
t_AA
t_BUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V_CC, until
Valid
SDA exits the 30% to 70% of V_CC window
Time the Bus Must be Free before the SDA crossing 70% of V_CC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of V_CC
during the following START condition
1300
900
ns
ns
t_LOW Clock LOW Time
Measured at the 30% of V_CC crossing
1300
ns
t_HIGH Clock HIGH Time
Measured at the 70% of V_CC crossing
600
ns
t_SU:STA START Condition Setup Time
SCL rising edge to SDA falling edge; both
600
ns
crossing 70% of V_CC
t_HD:STA START Condition Hold Time
From SDA falling edge crossing 30% of V_CC
600
ns
to SCL falling edge crossing 70% of V_CC
t_SU:DAT Input Data Setup Time
From SDA exiting the 30% to 70% of V_CC
100
ns
window, to SCL rising edge crossing 30% of
V_CC
t_HD:DAT Input Data Hold Time
From SCL rising edge crossing 70% of V_CC
0
ns
to SDA entering the 30% to 70% of V_CC
window
t_SU:STO STOP Condition Setup Time
From SCL rising edge crossing 70% of V_CC,
600
ns
to SDA rising edge crossing 30% of V_CC
t_HD:STO STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
1300
ns
or Volatile Only Write
both crossing 70% of V_CC
t_DH
Output Data Hold Time
From SCL falling edge crossing 30% of V_CC,
0
ns
until SDA enters the 30% to 70% of V_CC
window
t_R
SDA and SCL Rise Time
From 30% to 70% of V_CC
20 +
0.1*Cb
250
ns
t_F
SDA and SCL Fall Time
From 70% to 30% of V_CC
20 +
0.1*Cb
250
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
5
FN6310.1
September 9, 2009