ISL22319 Datasheet, PDF (11/13 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer XDCP

ISL22319
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
WRITE
S
T
A _{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
0 1 0 1 0 A1 A0 0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=0
FIGURE 14. BYTE WRITE SEQUENCE
ADDRESS
BYTE
S
T
A IDENTIFICATION
R _{BYTE WITH}
T
R/W=1
A
A
C
C
K
K
S
AT
CO
KP
SIGNAL AT SDA 0 1 0 1 0A1 A0 0 0 0 0 0
A
SIGNALS FROM
C
THE SLAVE
K
0 1 0 1 0 A1 A0 1
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
LAST READ
DATA BYTE
FIGURE 15. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22319 responds with an ACK. At this time, the device
enters its standby state (see Figure 14).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure15). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL22319 responds with an ACK. Then
the ISL22319 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK and STOP condition) following the
last bit of the last Data Byte (see Figure15).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
Applications Information
The typical application diagram is shown on Figure 16. For
proper operation adding 0.1µF decoupling ceramic capacitor
to V_CC is recommended. The capacitor value may vary
based on expected noise frequency of the design.
11
FN6310.1
September 9, 2009