82C54_05 Datasheet, PDF (5/22 Pages) Intersil Corporation – CMOS Programmable Intervel Timer

Functional Diagram
82C54
D₇ - D₀ 8
DATA/
BUS
BUFFER
RD
WR
READ/
WRITE
A₀
LOGIC
A₁
CS
CONTROL
WORD
REGISTER
Pin Description
DIP PIN
SYMBOL NUMBER
D7 - D0
1-8
CLK 0
9
OUT 0
10
GATE 0
11
GND
12
OUT 1
13
GATE 1
14
CLK 1
15
GATE 2
16
OUT 2
17
CLK 2
18
A0, A1
19 - 20
TYPE
I/O
I
O
I
O
I
I
I
O
I
I
COUNTER
0
COUNTER
1
CLK 0
GATE 0
OUT 0
CONTROL
WORD
REGISTER
CLK 1
GATE 1
OUT 1
CONTROL
LOGIC
STATUS
LATCH
STATUS
REGISTER
INTERNAL BUS
CR_M
CR_L
CE
COUNTER
2
CLK 2
GATE 2
OUT 2
GATE n
CLK n OUT n
OL_M
OL_L
COUNTER INTERNAL BLOCK DIAGRAM
DEFINITION
DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1
A0
SELECTS
0
0
Counter 0
0
1
Counter 1
1
0
Counter 2
1
1
Control Word Register
CS
21
RD
22
WR
23
V_CC
24
I
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR
are ignored otherwise.
I
READ: This input is low during CPU read operations.
I
WRITE: This input is low during CPU write operations.
-
V_CC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for
decoupling.
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