82C54_05 Datasheet, PDF (11/22 Pages) Intersil Corporation – CMOS Programmable Intervel Timer

82C54
COMMANDS
D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
RESULT
1
1
0
0
0
0
1
0 Read-Back Count and Status of Counter 0 Count and Status Latched for Counter 0
1
1
1
0
0
1
0
0 Read-Back Status of Counter 1
Status Latched for Counter 1
1
1
1
0
1
1
0
0 Read-Back Status of Counters 2, 1
Status Latched for Counter 2,
But Not Counter 1
1
1
0
1
1
0
0
0 Read-Back Count of Counter 2
Count Latched for Counter 2
1
1
0
0
0
1
0
0 Read-Back Count and Status of Counter 1 Count Latched for Counter 1,
But Not Status
1
1
1
0
0
0
1
0 Read-Back Status of Counter 1
Command Ignored, Status Already
Latched for Counter 1
FIGURE 7. READ-BACK COMMAND EXAMPLE
CS RD WR A1 A0
0 1 0 0 0 Write into Counter 0
0 1 0 0 1 Write into Counter 1
0 1 0 1 0 Write into Counter 2
0 1 0 1 1 Write Control Word
0 0 1 0 0 Read from Counter 0
0 0 1 0 1 Read from Counter 1
0 0 1 1 0 Read from Counter 2
0 0 1 1 1 No-Operation (Three-State)
1 X X X X No-Operation (Three-State)
0 1 1 X X No-Operation (Three-State)
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
MODE DEFINITIONS
The following are defined for use in describing the operation
of the 82C54.
CLK PULSE - A rising edge, then a falling edge, in that
order, of a Counter’s CLK input.
TRIGGER - A rising edge of a Counter’s Gate input.
COUNTER LOADING - The transfer of a count from the CR
to the CE (See “Functional Description”)
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is
written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte disables counting. Out is set low
immediately (no clock pulse required).
2. Writing the second byte allows the new count to be
loaded on the next CLK pulse.
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
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