82C54_05 Datasheet, PDF (4/22 Pages) Intersil Corporation – CMOS Programmable Intervel Timer

82C54
AC Electrical SpecificationsV_CC = +5.0V ± 10%, Includes all Temperature Ranges
82C54
82C54-10
SYMBOL
PARAMETER
MIN MAX MIN MAX
READ CYCLE
(1)
TAR Address Stable Before RD
30
-
25
-
(2)
TSR CS Stable Before RD
0
-
0
-
(3)
TRA Address Hold Time After RD
0
-
0
-
(4)
TRR RD Pulse Width
150
-
95
-
(5)
TRD Data Delay from RD
-
120
-
85
(6)
TAD Data Delay from Address
-
210
-
185
(7)
TDF RD to Data Floating
5
85
5
65
(8)
TRV Command Recovery Time
200
-
165
-
WRITE CYCLE
(9)
TAW Address Stable Before WR
0
-
0
-
(10)
TSW CS Stable Before WR
0
-
0
-
(11)
TWA Address Hold Time After WR
0
-
0
-
(12)
TWW WR Pulse Width
95
-
95
-
(13)
TDW Data Setup Time Before WR
140
-
95
-
(14)
TWD Data Hold Time After WR
25
-
0
-
(15)
TRV Command Recovery Time
200
-
165
-
CLOCK AND GATE
(16) TCLK Clock Period
125
DC
100
DC
(17) TPWH High Pulse Width
60
-
30
-
(18) TPWL Low Pulse Width
60
-
40
-
(19)
TR Clock Rise Time
-
25
-
25
(20)
TF Clock Fall Time
-
25
-
25
(21)
TGW Gate Width High
50
-
50
-
(22)
TGL Gate Width Low
50
-
50
-
(23)
TGS Gate Setup Time to CLK
50
-
40
-
(24)
TGH Gate Hold Time After CLK
50
-
50
-
(25)
TOD Output Delay from CLK
-
150
-
100
(26) TODG Output Delay from Gate
-
120
-
100
(27)
TWO OUT Delay from Mode Write
-
260
-
240
(28)
TWC CLK Delay for Loading
0
55
0
55
(29)
TWG Gate Delay for Sampling
-5
40
-5
40
(30)
TCL CLK Setup for Count Latch
-40
40
-40
40
NOTE:
1. Not tested, but characterized at initial design and at major process/design changes.
82C54-12
MIN MAX
TEST
UNITS CONDITIONS
25
-
ns
0
-
ns
0
-
ns
95
-
ns
-
85
ns
-
185
ns
5
65
ns
165
-
ns
1
1
1
1
1
1
2, Note 1
0
-
ns
0
-
ns
0
-
ns
95
-
ns
95
-
ns
0
-
ns
165
-
ns
80
DC
ns
1
30
-
ns
1
30
-
ns
1
-
25
ns
-
25
ns
50
-
ns
1
50
-
ns
1
40
-
ns
1
50
-
ns
1
-
100
ns
1
-
100
ns
1
-
240
ns
1
0
55
ns
1
-5
40
ns
1
-40
40
ns
1
4