X95840 Datasheet, PDF (4/13 Pages) Intersil Corporation – Quad Digital Controlled Potentiometers

X95840
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1) MAX
I_CC1
V_CC supply current
f_SCL = 400kHz; SDA = Open; (for 2-Wire,
1
(Volatile write/read)
Active, Read and Volatile Write States only)
I_CC2
V_CC supply current
f_SCL = 400kHz; SDA = Open; (for 2-Wire,
3
(nonvolatile write)
Active, Nonvolatile Write State only)
I_SB
V_CC current (standby)
V_CC = +5.5V, 2 Wire Interface in Standby State
5
V_CC = +3.6V, 2 Wire Interface in Standby State
2
I_LkgDig
Leakage current, at
Voltage at pin from GND to V_CC
pins A0, A1, A2, SDA, SCL,
and WP pins
-10
10
t_DCP
DCP wiper response time SCL falling edge of last bit of DCP Data Byte to wiper
1
(Note 15)
change
Vpor
Power-on recall voltage
Minimum V_CC at which memory recall occurs
1.8
2.6
VccRamp V_CC ramp rate
0.2
t_D (Note 15) Power up delay
V_CC above Vpor, to DCP Initial Value Register recall
3
completed, and 2-Wire Interface in standby state
EEPROM SPECS
EEPROM Endurance
150,000
EEPROM Retention
Temperature ≤ 75°C
50
SERIAL INTERFACE SPECS
V_IL
WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
-0.3
0.3*Vcc
V_IH
WP, A2, A1, A0, SDA, and
SCL input buffer HIGH
voltage
0.7*Vcc
Vcc+0.3
Hysteresis SDA and SCL input buffer
(Note 15) hysteresis
0.05*
Vcc
V_OL (Note 15) SDA output buffer LOW
voltage, sinking 4 mA
0
0.4
Cpin
WP, A2, A1, A0, SDA, and
10
(Note 15) SCL pin capacitance
f_SCL
SCL frequency
400
t_IN (Note 15) Pulse width suppression time Any pulse narrower than the max spec is suppressed.
50
at SDA and SCL inputs
t_AA (Note 15) SCL falling edge to SDA
SCL falling edge crossing 30% of V_CC, until SDA exits
900
output data valid
the 30% to 70% of V_CC window.
t_BUF
(Note 15)
Time the bus must be free
before the start of a new
transmission
SDA crossing 70% of V_CC during a STOP condition, to
SDA crossing 70% of V_CC during the following START
condition.
1300
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
Clock LOW time
Measured at the 30% of V_CC crossing.
Clock HIGH time
Measured at the 70% of V_CC crossing.
START condition setup time SCL rising edge to SDA falling edge. Both crossing
70% of V_CC.
START condition hold time From SDA falling edge crossing 30% of V_CC to SCL
falling edge crossing 70% of V_CC.
1300
600
600
600
UNITS
mA
mA
µA
µA
µA
µs
V
V/ms
ms
Cycles
Years
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
4
FN8213.1
September 27, 2005