X95840 Datasheet, PDF (2/13 Pages) Intersil Corporation – Quad Digital Controlled Potentiometers

Block Diagram
X95840
SDA
SCL
2-wire
Interface
Power-up,
Interface,
Control and
Status Logic
A2
A1
A0
Non-Volatile
Registers
V_CC
WR3
WR2
WR1
WR0
DCP3
DCP2
DCP1
DCP0
R_H3
R_W3
R_L3
R_H2
R_W2
R_L2
R_H1
R_W1
R_L1
R_H0
R_W0
R_L0
Pin Descriptions
TSSOP PIN
SYMBOL
1
RH3
2
RL3
3
RW3
4
A2
5
SCL
6
SDA
7
GND
8
RW2
9
RL2
10
RH2
11
RW1
12
RL1
13
RH1
14
A0
15
A1
16
V_CC
17
WP
18
RH0
19
RL0
20
RW0
WP
GND
DESCRIPTION
“High” terminal of DCP3
“Low” terminal of DCP3
“Wiper” terminal of DCP3
Device address for the 2-wire interface
2-wire interface clock
Serial data I/O for the 2-wire interface
Device ground pin
“Wiper” terminal of DCP2
“Low” terminal of DCP2
“High” terminal of DCP2
“Wiper” terminal of DCP1
“Low” terminal of DCP1
“High” terminal of DCP1
Device address for the 2-wire interface
Device address for the 2-wire interface
Power supply pin
Hardware write protection pin. Active low. Prevents any “Write” operation of the 2-wire interface.
“High” terminal of DCP0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
2
FN8213.1
September 27, 2005