X9401_15 Datasheet, PDF (4/20 Pages) Intersil Corporation – Quad, 64 Tap, Digitally Controlled Potentiometer

X9401
Array Description
The X9401 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V_H/R_H
and V_L/R_L inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V_W/R_W)
output. Within each individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers, one for
each XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of sixty-four switches along its resistor
array. The contents of the WCR can be altered in four ways:
it may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
Global XFR Data Register instructions (parallel load); it can
be modified one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its data
register zero (R0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9401 is powered-down.
Although the register is automatically loaded with the value
in R₀ upon power-up, this may be different from the value
present at power-down. The wiper position must be stored in
R₀ to insure restoring the wiper position after power-up.
Data Registers
Each potentiometer has four 6-bit nonvolatile data registers.
These can be read or written directly by the host. Data can
also be transferred between any of the four data registers
and the associated Wiper Counter Register. All operations
changing data in one of the data registers is a nonvolatile
operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can be used
as memory locations for system parameters or user
preference data.
DATA REGISTER DETAIL
(MSB)
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
Write in Process
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command.
Instructions
Identification (ID) Byte
The first byte sent to the X9401 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The
most significant four bits of the slave address are a device
type identifier. For the X9401 this is fixed as 0101[B] (refer to
Figure 1).
The two least significant bits in the ID byte select one of four
devices on the bus. The physical device address is defined
by the state of the A₀ - A₁ input pins. The X9401 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for the
X9401 to successfully continue the command sequence.
The A₀ - A₁ inputs can be actively driven by CMOS input
signals or tied to V_CC or V_SS. The remaining two bits in the
slave byte must be set to 0.
DEVICE TYPE
IDENTIFIER
0
1
0
10
0
A1 A0
DEVICE ADDRESS
FIGURE 1. IDENTIFICATION BYTE FORMAT
Instruction Byte
The next byte sent to the X9401 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the four pots
and, when applicable, they point to one of four associated
registers. The format is shown below in Figure 2.
4
FN8190.5
September 14, 2015