ISL78010_14 Datasheet, PDF (4/19 Pages) Intersil Corporation – Automotive Grade TFT-LCD Power Supply

ISL78010
Electrical Specifications
V_DD = 5V, V_BOOST = 11V, I_LOAD = 200mA, V_ON = 15V, V_OFF = -5V, V_LOGIC = 2.5V, limits over -40°C to
+105°C temperature range, unless otherwise specified. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
(Note 6) TYP (Note 6) UNIT
FAULT DETECTION
t_FAULT
OT
Fault Time Out
Over-temperature Threshold
C_DLY = 0.22µF
50
ms
140
°C
I_PG
PG Pull-down Current
VPG > 0.6V
VPG < 0.6V
15
µA
1.7
mA
LOGIC ENABLE
V_HI
Logic High Threshold
2.3
V
V_LO
Logic Low Threshold
0.8
V
I_LOW
Logic Low Bias Current
0.2
2
µA
I_HIGH
Logic High Bias Current
at V_EN = 5V
12
18
24
µA
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Pin Descriptions
PIN NAME
PIN NUMBER
1, 2, 4, 6, 8, 10, 12,
16, 18, 23, 32
3
NC
DELB
5
LX
7
DRVP
9
FBP
11
DRVL
13
FBL
14, 27
SGND
15
DRVN
17
FBN
19, 20, 21, 22
PGND
24
VREF
25
CINT
26
FBB
28
EN
29
VDD
30
PG
31
CDLY
Not connected
DESCRIPTION
Open drain output for gate drive of optional V_BOOST delay FET
Drain of the internal N-Channel boost FET
Positive LDO base drive; open drain of an internal N-Channel FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Logic LDO base drive; open drain of an internal N-Channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
Negative LDO base drive; open drain of an internal P-Channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N-Channel boost FET
Bandgap reference output voltage; bypass with a 0.1µF to SGND
V_BOOST integrator output; connect capacitor to SGND for PI-mode or connect to V_DD for P-mode
operation
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin; High = Enable; Low or floating = Disable
Positive supply
Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been
detected, this is high
A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault
timeout time
4
FN6501.2
December 4, 2013