ISL78010_14 Datasheet, PDF (15/19 Pages) Intersil Corporation – Automotive Grade TFT-LCD Power Supply

ISL78010
Equation 17 gives the boundary between discontinuous and
continuous boost operation. Continuous operation (LX
switching every clock cycle) requires:
I_{--A----V----D----D-----}(_--l_--o_----a_----d_---)_---->_-----D_-----×_-----(_---1_{----–-----}D_-----)_---×_-----V_----I--N--
2 × L × f_OSC
(EQ. 17)
where the duty cycle, D = (A_VDD - V_IN)/A_VDD
For example, with V_IN = 5V, f_OSC = 1.0MHz and
A_VDD = 12V, continuous operation of the boost converter
can be guaranteed as shown in Equations 18, 19, and 20:
L = 10μH and I_AVDD > 61mA
(EQ. 18)
L = 6.8μH and I_AVDD > 89mA
(EQ. 19)
L = 3.3μH and I_AVDD > 184mA
(EQ. 20)
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
calculated as shown in Equation 21:
C_O
U
T
≥
---------------------^I--^O----^U-----^T----------------------
2 × V_RIPPLE × f_OSC
(EQ. 21)
where f_OSC is the switching frequency.
Start-Up Sequence
Figure 28 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V_CDLY.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input voltage is higher than 2.5V, an internal
current source starts to charge C_CDLY to an upper threshold
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
condition. If no fault is found, C_CDLY is discharged after the
first peak, and V_REF turns on.
During the second ramp, the device checks the status of
V_REF and over-temperature. At the peak of the second
ramp, PG output goes low and enables the input protection
PMOS Q₁. Q₁ is a controlled FET used to prevent in-rush
current into V_BOOST before V_BOOST is enabled internally.
Its rate of turn-on is controlled by C_o. When a fault is
detected, M1 will turn off and disconnect the inductor from
V_IN.
With the input protection FET on, NODE1 (see “Typical
Application Diagram” on page 18) will rise to ~V_IN. Initially
the boost is not enabled, so V_BOOST rises to V_IN-V_DIODE
through the output diode. Hence, there is a step at V_BOOST
during this part of the start-up sequence. If this step is not
desirable, an external P-MOSFET can be used to delay the
output until the boost is enabled internally. The delayed
output appears at A_VDD.
V_BOOST soft-starts at the beginning of the third ramp. The
soft-start ramp depends on the value of the C_DLY capacitor.
For C_DLY of 220nF, the soft-start time is ~2ms.
V_REF and V_LOGIC turn on when input voltage (V_DD)
exceeds 2.5V. When a fault is detected, the outputs and the
input protection will turn off but V_REF will stay on.
V_OFF turns on at the start of the fourth peak. At the fifth
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q₄ to generate a delayed V_BOOST output.
V_ON is enabled at the beginning of the sixth ramp. A_VDD,
PG, V_OFF, DELB and V_ON are checked at end of this ramp.
Fault Protection
During the start-up sequence, prior to BOOST soft-start,
V_REF is checked to be within ±20% of its final value, and the
device temperature is checked. If either of these is not within
the expected range, the part is disabled until the power is
recycled or EN is toggled.
If C_DELAY is shorted low, then the sequence will not start,
while if C_DELAY is shorted H, the first down ramp will not
occur and the sequence will not complete.
Once the start-up sequence is completed, the chip
continuously monitors C_DLY, DELB, FBP, FBL, FBN, V_REF,
FBB, and PG, and checks for faults. During this time, the
voltage on the C_DLY capacitor remains at 1.15V until either a
fault is detected or the EN pin is pulled low.
A fault on C_DELAY, V_REF, or temperature will shut down the
chip immediately. If a fault on any other output is detected,
C_DELAY will ramp up linearly with a 5µA (typical) current to
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C_DLY capacitor returns to 1.15V.
Typical fault thresholds for FBP, FBL, FBN, and FBB are
included in the “Electrical Specifications” table beginning on
page 2. PG and DELB fault thresholds are typically 0.6V.
C_INT has an internal current-limited clamp to keep the
voltage within its normal range. If C_INT is shorted low, the
boost regulator will attempt to regulate to 0V. If C_INT is
shorted H, the regulator switches to P mode.
If any of the regulated outputs (V_BOOST, V_ON, V_OFF or
V_LOGIC) are driven above their target levels, the drive
circuitry will switch off until the output returns to its expected
value.
15
FN6501.2
December 4, 2013