ISL78010_14 Datasheet, PDF (17/19 Pages) Intersil Corporation – Automotive Grade TFT-LCD Power Supply

ISL78010
If V_BOOST is excessively loaded, the current limit will
prevent damage to the chip. While in current limit, the part
acts like a current source, and the regulated output will drop.
If the output drops below the fault threshold, a ramp will be
initiated on C_DELAY and, provided the fault is sustained, the
chip will be disabled upon completion of the ramp.
In some circumstances (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.
All I/O also has ESD protection, which in many cases will
also provide overvoltage protection relative to either ground
or VDD. However, these will not generally operate unless
absolute maximum ratings are exceeded.
Component Selection for Start-Up Sequencing and
Fault Protection
The C_REF capacitor is typically set at 220nF and is required
to stabilize the V_REF output. The range of C_REF is from
22nF to 1µF and should not be more than five times the
capacitor on C_DEL to ensure correct start-up operation.
The C_DEL capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads. It is
limited only by leakage in the capacitor reaching µA levels.
C_DEL should be at least 1/5 of the value of C_REF. Note that
with 220nF on C_DEL the fault time-out will typically be 50ms,
and the use of a larger or smaller value will vary this time
proportionally (e.g., 1µF will give a fault time-out period of
typically 230ms).
Fault Sequencing
The ISL78010 has advanced fault detection systems which
protect the IC from both adjacent pin shorts during operation
and shorts on the output supplies.
A high-quality layout and design of the PCB with respect to
grounding and decoupling is necessary to avoid falsely
triggering the fault detection scheme, especially during
start-up. See “Layout Recommendation” on page 17 and
“Component Selection for Start-Up Sequencing and Fault
Protection” on page 17 to avoid problems during initial
evaluation and prototype PCB generation.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. If the die temperature exceeds the thermal
trip point of +140°C, the device will shut down.
Layout Recommendation
Device performance, including efficiency, output noise,
transient response and control loop stability, is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
Some general guidelines for layout include:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place V_REF and V_DD bypass capacitors close to the pins.
3. Minimize the length of traces carrying fast signals and
high current.
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
6. A signal ground plane, separate from the power ground
plane, should be used for ground return connections for
feedback resistor networks (R₁, R₁₁, R₄₁) and the V_REF
capacitor, C₂₂; the C_DELAY capacitor, C₇; and the
integrator capacitor, C₂₃.
7. Minimize feedback input track lengths to avoid switching
noise pickup.
8. Connect all "NC" pins to the ground plane to improve
thermal performance and switching noise immunity
between pins.
An evaluation board, ISL78010EVAL1Z, is available to
illustrate the proper layout implementation. See “Ordering
Information” on page 1.
17
FN6501.2
December 4, 2013