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ISL12025 Datasheet, PDF (4/27 Pages) Intersil Corporation – Real-Time Clock/Calendar with I2C Bus and EEPROM
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ISL12025
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 12) (Note 5) (Note 12)
tRPD VDD Detect to RESET LOW
tPURST Power-up Reset Time-Out Delay
VRVALID Minimum VDD for Valid RESET
Output
500
100
250
400
1.0
VRESET ISL12025-4.5A Reset Voltage
Level
4.59
4.64
4.69
ISL12025 Reset Voltage Level
4.33
4.38
4.43
ISL12025-3 Reset Voltage Level
3.04
3.09
3.14
ISL12025-2.7A Reset Voltage
Level
2.87
2.92
2.97
ISL12025-2.7 Reset Voltage Level
2.58
2.63
2.68
tWDO Watchdog Timer Period
32.768kHz crystal between X1 and X2 1.70
725
1.75
1.801
750
775
225
250
275
tRST Watchdog Timer Reset Time-Out 32.768kHz crystal between X1 and X2 225
250
275
Delay
tRSP I2C Interface Minimum Restart
1.2
Time
EEPROM SPECIFICATIONS
EEPROM Endurance
2,000,000
EEPROM Retention
Temperature ≤+75°C
50
UNITS
ns
ms
V
V
V
V
V
V
s
ms
ms
ms
µs
Cycles
Years
NOTES
9
Serial Interface (I2C) Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
(Note 12) TYP (Note 12) UNITS NOTES
VIL SDA and SCL Input Buffer LOW SBIB = 1 (Under VDD mode)
-0.3
Voltage
0.3xVDD
V
VIH SDA and SCL Input Buffer HIGH SBIB = 1 (Under VDD mode)
Voltage
0.7xVDD
VDD + 0.3
V
Hysteresis SDA and SCL Input Buffer
SBIB = 1 (Under VDD mode)
0.05xVDD
V
Hysteresis
VOL SDA Output Buffer LOW Voltage
ILI Input Leakage Current on SCL
ILO I/O Leakage Current on SDA
TIMING CHARACTERISTICS
IOL = 4mA
VIN = 5.5V
VIN = 5.5V
0
0.4
V
0.1
10
µA
0.1
10
µA
fSCL
tIN
SCL Frequency
Pulse Width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs
spec is suppressed.
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
Time the Bus Must Be Free before SDA crossing 70% of VDD during a
the Start of a New Transmission STOP condition, to SDA crossing
70% of VDD during the following
START condition.
1300
900
ns
ns
4
FN6371.3
August 13, 2008
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