ISL12025 Datasheet, PDF (10/27 Pages) Intersil Corporation – Real-Time Clock/Calendar with I2C Bus and EEPROM

ISL12025
DW: Day of the Week Register
This register provides a Day of the Week status and uses
three bits DY2 to DY0 to represent the seven days of the
week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value
to a specific day of the week is arbitrary and may be decided
by the system software designer. The default value is
defined as ‘0’.
Y2K: Year 2000 Register
Can have value 19 or 20. As of the date of the introduction of
this device, there would be no real use for the value 19 in a
true real-time clock, however.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and
H21 bit functions as an AM/PM indicator with a ‘1’,
representing PM. The clock defaults to standard time with
H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4.
Status Register (SR) (Volatile)
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
ADDR 7
65
43
2
1
0
003Fh BAT AL1 AL0 OSCF 0 RWEL WEL RTCF
Default 0
00
00
0
0
1
BAT: Battery Supply
This bit set to “1” indicates that the device is operating from
V_BAT, not V_DD. It is a read-only bit and is set/reset by
hardware (ISL12025 internally). Once the device begins
operating from V_DD, the device sets this bit to “0”.
AL1, AL0: Alarm Bits
These bits announce if either alarm 0 or alarm 1 match the
real-time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read
operation resets the flags. Note: Only the AL bits that are set
when an SR read starts will be reset. An alarm bit that is set
by an alarm occurring during an SR read operation will
remain set after the read operation is complete.
OSCF: Oscillator Fail Indicator
This bit is set to “1” if the oscillator is not operating, or is
operating but has clock jitter which does not affect the
accuracy of RTC counting. The bit is set to “0” if the oscillator
is functioning and does not have clock jitter. This bit is read
only, and is set/reset by hardware.
RWEL: Register Write Enable Latch
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit do
not cause a non-volatile write cycle, so the device is ready
for the next operation immediately after the stop condition. A
write to the CCR requires both the RWEL and WEL bits to be
set in a specific sequence.
WEL: Write Enable Latch
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the
LOW (disabled) state. While the WEL bit is LOW, writes to
the CCR address will be ignored, although acknowledgment
is still issued. The WEL bit is set by writing a “1” to the WEL
bit and zeroes to the other bits of the Status Register. Once
set, WEL remains set until either reset to 0 (by writing a “0”
to the WEL bit and zeroes to the other bits of the Status
Register) or until the part powers up again. Writes to WEL bit
do not cause a non-volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real-Time Clock Fail Bit
This bit is set to a ‘1’ after a total power failure. This is a read
only bit that is set internally when the device powers up after
having lost all power to the device (both V_DD and V_BAT = 0V).
The bit is set regardless of whether V_DD or V_BAT is applied
first. The loss of only one of the supplies does not result in
setting the RTCF bit. The first valid write to the RTC after a
complete power failure (writing one byte is sufficient) resets
the RTCF bit to ‘0’.
Unused Bits:
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit
location.
10
FN6371.3
August 13, 2008