ISL12025 Datasheet, PDF (2/27 Pages) Intersil Corporation – Real-Time Clock/Calendar with I2C Bus and EEPROM

Block Diagram
X1
32.768KHZ
X2
ISL12025
OSC COMPENSATION
OSCILLATOR
FREQUENCY
DIVIDER
1Hz
TIMER
CALENDAR
LOGIC
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
V_DD
V_BAT
SCL
SDA
SERIAL
INTERFACE
DECODER
CONTROL
DECODE
LOGIC
CONTROL/
REGISTERS
(EEPROM)
STATUS
REGISTERS
(SRAM)
ALARM
8
RESET
WATCHDOG LOW VOLTAGE
TIMER
RESET
COMPARE
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
Pin Descriptions
PIN NUMBER
SOIC
TSSOP
1
3
2
4
3
5
4
6
5
7
6
8
7
1
8
2
SYMBOL
BRIEF DESCRIPTION
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
RESET
RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period
has expired or that the voltage has dropped below a fixed V_TRIP threshold. It is an open drain active LOW
output. Recommended value for the pull-up resistor is 5kΩ. If unused, connect to ground.
GND Ground.
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
V_BAT
V_DD
This input provides a backup supply voltage to the device. V_BAT supplies power to the device in the event
that the V_DD supply fails. This pin should be tied to ground if not used.
Power Supply.
2
FN6371.3
August 13, 2008