ISL12025 Datasheet, PDF (17/27 Pages) Intersil Corporation – Real-Time Clock/Calendar with I2C Bus and EEPROM

ISL12025
SCL
SDA
START
STOP
FIGURE 17. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
1
DATA OUTPUT
FROM TRANSMITTER
8
9
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
DEVICE IDENTIFIER
ARRAY
CCR
1
0
1
0
1
1
0
1
1
1
1
R/W
0
0
0
0
0
0
0
A8
A7
A6
A5
A4
A3
A2
A1
A0
SLAVE ADDRESS BYTE
BYTE 0
WORD ADDRESS 1
BYTE 1
WORD ADDRESS 0
BYTE 2
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
BYTE 3
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first 4-bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
17
FN6371.3
August 13, 2008