DG201 Datasheet, PDF (4/7 Pages) Intersil Corporation – CMOS Quad SPST Analog Switch

Test Circuits
3V
0V
LOGIC
INPUT
DG201
ANALOG
INPUT 10V
10pF
V_OUT
1kΩ
3V
0V
LOGIC
INPUT
ANALOG
INPUT 10V
10nF
V_OUT
FIGURE 1. t_ON AND t_OFF TEST CIRCUIT
FIGURE 2. CHARGE INJECTION TEST CIRCUIT
LOGIC
INPUT
3V
ANALOG INPUT
2V_P-P AT 1MHz
V_OUT
100Ω
51Ω
FIGURE 3. OFF ISOLATION TEST CIRCUIT
Typical Applications
Using the V_REF Terminal
The DG201 has an internal voltage divider setting the TTL
threshold on the input control lines for V+ equal to +15V. The
schematic shown in Figure 4 with nominal resistor values,
gives approximately 2.4V on the V_REF pin. As the TTL input
signal goes from +0.8V to +2.4V, Q₁ and Q₂ switch states to
turn the switch ON and OFF. If the power supply voltage is
less than +15V, then a resistor (R_EXT) must be added
between V+ and the V_REF pin, to restore +2.4V at V_REF.
The table shows the value of this resistor for various supply
voltages, to maintain TTL compatibility. If CMOS logic levels
with a +5V supply are being used, the threshold shifts are
less critical, but a separate column of suitable values is given
in the table. For logic swings of -5V to + 5V, no resistor is
needed.
In general, the “low” logic level should be <0.8V to prevent
Q₁ and Q₂ from both being ON together (this will cause
incorrect switch function).
V+ SUPPLY (V)
+15
+12
+10
+9
+8
+7
TABLE 1.
R_EXT FOR TTL
LEVELS (kΩ)
-
420
190
136
98
70
R_EXT FOR CMOS
LEVELS (kΩ)
-
-
-
136
98
70
Q₁
INPUT
V+
118kΩ
V_REF
23kΩ
GATE
PROTECTION
RESISTOR
FIGURE 4.
R_EXT
Q₂
4