82C284 Datasheet, PDF (4/11 Pages) Intersil Corporation – Clock Generator and Ready Interface for 80C286 Processors

82C284
CLK
PCLK
1
φ1
φ2
φ1
φ2
2
φ1
φ2
F/C
EFI
3
FIGURE 1B. F/C SWITCHED FROM LOW (USING THE CRYSTAL INPUT X1) TO HIGH (USING THE EFI INPUT)
FIGURE 1. DYNAMICALLY SWITCHING THE F/C PIN
The 82C284 provides a second clock output, PCLK, for periph-
eral devices. PCLK is CLK divided by two. PCLK has a duty
cycle of 50% and CMOS output drive characteristics. PCLK is
normally synchronized to the internal processor clock.
After reset, the PCLK signal may be out of phase with the inter-
nal processor clock. The S1 and S0 signals of the first bus
cycle are used to synchronize PCLK to the internal processor
clock. The phase of the PCLK output changes by extending its
HIGH time beyond one system clock (see waveforms). PCLK is
forced HIGH whenever either S0 or S1 were active (LOW) for
the two previous CLK cycles. PCLK continues to oscillate when
both S0 and S1 are HIGH.
Since the phase of the internal processor clock will not change
except during reset, the phase of PCLK will not change except
during the first bus cycle after reset.
Oscillator
The oscillator circuit of the 82C284 is a linear Pierce oscillator
which requires an external parallel resonant, fundamental
mode, crystal. The output of the oscillator is internally buffered.
The crystal frequency chosen should be twice the required
internal processor clock frequency. The crystal should have a
typical load capacitance of 32pF.
X1 and X2 are the oscillator crystal connections. For stable
operation of the oscillator, two loading capacitors are recom-
mended, as shown in Table 1. The sum of the board capaci-
tance and loading capacitance should equal the values shown.
It is advisable to limit stray board capacitances (not including
the effect of the loading capacitors or crystal capacitance) to
less than 10pF between the X1 and X2 pins. Decouple V_CC
and GND as close to the 82C284 as possible with a 0.1µF poly-
carbonate capacitor.
TABLE 1. 82C284 CRYSTAL LOADING CAPACITANCE VALUES
CRYSTAL
FREQUENCY
1MHz to 8MHz
8MHz to 20MHz
20MHz to 25MHz
Cl
CAPACITANCE
(PIN 7)
60pF
25pF
15pF
C2
CAPACITANCE
(PIN 8)
40pF
15pF
15pF
CLK Termination
Due to the CLK output having a very fast rise and fall time, it is
recommended to properly terminate the CLK line at frequen-
cies above 10MHz to avoid signal reflections and ringing. Ter-
mination is accomplished by inserting a small resistor
(typically 10-74Ω) in series with the output, as shown in Figure
2. This is known as series termination. The resistor value plus
the circuit output impedance (approximately 25Ω) should be
made equal to the impedance of the transmission line.
CLK
OUT
RO ≈ 25
R
Z
TRANSMISSION
LINE
Z
CLOSELY
PLACED
LOADS
CLOSELY
PLACED
LOADS
FIGURE 2. SERIES TERMINATION
Reset Operation
The reset logic provides the RESET output to force the sys-
tem into a known, initial state. When the RES input is active
(LOW), the RESET output becomes active (HIGH), RES is
synchronized internally at the falling edge of CLK before
generating the RESET output (see waveforms). Synchroni-
zation of the RES input introduces a one or two CLK delay
before affecting the RESET Output.
At power up, a system does not have a stable V_CC and CLK.
To prevent spurious activity, RES should be asserted until
V_CC and CLK stabilize at their operating values. 80C286
processors and support components also require their
RESET inputs be HIGH a minimum of 16 CLK cycles. An RC
network, as shown in Figure 3, will keep RES LOW long
enough to satisfy both needs.
A Schmitt trigger input with hysteresis on RES assures a single
transition of RESET with an RC circuit on RES. The hysteresis
separates the input voltage level at which the circuit output
switches from HIGH to LOW from the input voltage level at
which the circuit output switches from LOW to HIGH. The RES
HIGH to LOW input transition voltage is lower than the RES
4