82C284 Datasheet, PDF (1/11 Pages) Intersil Corporation – Clock Generator and Ready Interface for 80C286 Processors

82C284
March 1997
Clock Generator and Ready Interface
for 80C286 Processors
Features
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt
Trigger Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
• Dynamically Switchable between Two Input
Frequencies
• Provides Local READY and MULTIBUS^® READY
Synchronization
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CerDIP Package
Description
The Intersil 82C284 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with
hysteresis.
Ordering Information
PART NUMBER
CD82C284-12
ID82C284-10
ID82C284-12
TEMP. RANGE
0^oC to +70^oC
-40^oC to +85^oC
-40^oC to +85^oC
PACKAGE
PKG.
NO.
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP)
TOP VIEW
ARDY 1
SRDY 2
SRDYEN 3
READY 4
EFI 5
F/C 6
X1 7
X2 8
GND 9
18 VCC
17 ARDYEN
16 S1
15 S0
14 NC
13 PCLK
12 RESET
11 RES
10 CLK
Functional Diagram
RES
X1
X2
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
S1
S0
RESET
SYNCHRONIZER
XTAL
OSC
MUX
SYNCHRONIZER
READY LOGIC
PCLK GENERATOR
RESET
CLK
READY
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
MULTIBUS^® is a patented Intel bus.
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File Number 2966.1