ISL6236 Datasheet, PDF (34/35 Pages) Intersil Corporation – High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers

ISL6236
Mount all of the power components on the top side of the board
with their ground terminals flush against one another, if
possible. Follow these guidelines for good PC board layout:
• Isolate the power components on the top side from the
sensitive analog components on the bottom side with a
ground shield. Use a separate PGND plane under the
OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid
the introduction of AC currents into the PGND1 and PGND2
ground planes. Run the power plane ground currents on the
top side only, if possible.
• Use a star ground connection on the power plane to
minimize the crosstalk between OUT1 and OUT2.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
• Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick copper
PC boards (2oz vs 1oz) can enhance full-load efficiency
by 1% or more. Correctly routing PC board traces must be
approached in terms of fractions of centimeters, where a
single mΩ of excess trace resistance causes a
measurable efficiency penalty.
• PHASE (ISL6236) and GND connections to the
synchronous rectifiers for current limiting must be made
using Kelvin-sense connections to guarantee the
current-limit accuracy with 8 Ld SO MOSFETs. This is best
done by routing power to the MOSFETs from outside using
the top copper layer, while connecting PHASE traces
inside (underneath) the MOSFETs.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be made
longer than the discharge path. For example, it is better to
allow some extra distance between the input capacitors
and the high-side MOSFET than to allow distance
between the inductor and the synchronous rectifier or
between the inductor and the output filter capacitor.
• Ensure that the OUT connection to COUT is short and
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the OUT
connector node and the output filter capacitor.
• Route high-speed switching nodes (BOOT, UGATE,
PHASE, and LGATE) away from sensitive analog areas
(REF, ILIM, and FB). Use PGND1 and PGND2 as an EMI
shield to keep radiated switching noise away from the IC's
feedback divider and analog bypass capacitors.
• Make all pin-strap control input connections (SKIP, ILIM,
etc.) to GND or VCC of the device.
Layout Procedure
Place the power components first with ground terminals
adjacent (Q₂/Q₄ source, C_IN, C_OUT). If possible, make all
these connections on the top layer with wide, copper-filled
areas.
Mount the controller IC adjacent to the synchronous rectifier
MOSFETs close to the hottest spot, preferably on the back
side in order to keep UGATE, GND, and the LGATE gate
drive lines short and wide. The LGATE gate trace must be
short and wide, measuring 50 mils to 100 mils wide if the
MOSFET is 1” from the controller device.
Group the gate-drive components (BOOT capacitor, VIN
bypass capacitor) together near the controller device.
Make the DC/DC controller ground connections as follows:
1. Near the device, create a small analog ground plane.
2. Connect the small analog ground plane to GND and use
the plane for the ground connection for the REF and VCC
bypass capacitors, FB dividers and ILIM resistors (if any).
3. Create another small ground island for PGND and use
the plane for the VIN bypass capacitor, placed very close
to the device.
4. Connect the GND and PGND planes together at the
metal tab under device.
On the board's top side (power planes), make a star ground
to minimize crosstalk between the two sides. The top-side
star ground is a star connection of the input capacitors and
synchronous rectifiers. Keep the resistance low between the
star ground and the source of the synchronous rectifiers for
accurate current limit. Connect the top-side star ground
(used for MOSFET, input, and output capacitors) to the small
island with a single short, wide connection (preferably just a
via). Create PGND islands on the layer just below the
topside layer (refer to the ISL6236 Evaluation Kit Application
Notes, AN1271 and AN1272) to act as an EMI shield if
multiple layers are available (highly recommended). Connect
each of these individually to the star ground via, which
connects the top side to the PGND plane. Add one more
solid ground plane under the device to act as an additional
shield, and also connect the solid ground plane to the star
ground via.
Connect the output power planes (VCORE and system
ground planes) directly to the output filter capacitor positive
and negative terminals with multiple vias.
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FN6373.6
April 29, 2010