ISL6236 Datasheet, PDF (26/35 Pages) Intersil Corporation – High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers

ISL6236
full-load efficiency (assuming that the coil resistance remains
fixed) and less output voltage ripple. Penalties for using
higher inductor values include larger physical size and
degraded load-transient response (especially at low
input-voltage levels).
DC output accuracy specifications refer to the trip level of the
error comparator. When the inductor is in continuous
conduction, the output voltage has a DC regulation higher
than the trip level by 50% of the ripple. In discontinuous
conduction (SKIP = GND, light load), the output voltage has
a DC regulation higher than the trip level by approximately
1.0% due to slope compensation.
Forced-PWM Mode
The low-noise, forced-PWM (SKIP = VCC) mode disables
the zero-crossing comparator, which controls the low-side
switch ON-time. Disabling the zero-crossing detector causes
the low-side, gate-drive waveform to become the
complement of the high-side, gate-drive waveform. The
inductor current reverses at light loads as the PWM loop
strives to maintain a duty ratio of V_OUT/V_IN. The benefit of
forced-PWM mode is to keep the switching frequency fairly
constant, but it comes at a cost: the no-load battery current
can be 10mA to 50mA, depending on switching frequency
and the external MOSFETs.
Forced-PWM mode is most useful for reducing
audio-frequency noise, improving load-transient response,
providing sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of
multiple-output applications that use a flyback transformer or
coupled inductor.
Enhanced Ultrasonic Mode
(25kHz (min) Pulse Skipping)
Leaving SKIP unconnected or connecting SKIP to REF
activates a unique pulse-skipping mode with a minimum
switching frequency of 25kHz. This ultrasonic pulse-skipping
mode eliminates audio-frequency modulation that would
otherwise be present when a lightly loaded controller
automatically skips pulses. In ultrasonic mode, the controller
automatically transitions to fixed-frequency PWM operation
when the load reaches the same critical conduction point
(ILOAD(SKIP)).
An ultrasonic pulse occurs when the controller detects that
no switching has occurred within the last 20µs. Once
triggered, the ultrasonic controller pulls LGATE high, turning
on the low-side MOSFET to induce a negative inductor
current. After FB drops below the regulation point, the
controller turns off the low-side MOSFET (LGATE pulled low)
and triggers a constant ON-time (UGATE driven high). When
the ON-time has expired, the controller re-enables the
low-side MOSFET until the controller detects that the
inductor current dropped below the zero-crossing threshold.
Starting with a LGATE pulse greatly reduces the peak output
voltage when compared to starting with a UGATE pulse, as
long as VFB < VREF, LGATE is off and UGATE is on, similar
to pure SKIP mode.
40µs (MAX)
INDUCTOR
CURRENT
0A
FB<ReFgB.P<oRiEntG.POINT
ZeErRoO-C-CroRsOsSinSgING
DeDteEcTtiEoCnTION
ON-TIME (t_ON)O) _N)
FIGURE 72. ULTRASONIC CURRENT WAVEFORMS
Reference and Linear Regulators (VREF3,
REF, LDO and 14V Charge Pump)
The 3.3V reference (VREF3) is accurate to ±1.5%
over-temperature, making VREF3 useful as a precision
system reference. VREF3 can supply up to 5mA for external
loads. Bypass VREF3 to GND with a 0.01µF capacitor.
Leave it open if there is no load.
The 2V reference (REF) is accurate to ±1% over-temperature,
also making REF useful as a precision system reference.
Bypass REF to GND with a 0.1µF (min) capacitor. REF can
supply up to 50µA for external loads.
An internal regulator produces a fixed 5V
(LDOREFIN < 0.2V) or 3.3V (LDOREFIN > VCC - 1V). In an
adjustable mode, the LDO output can be set from 0.7V to
4.5V. The LDO output voltage is equal to two times the
LDOREFIN voltage. The LDO regulator can supply up to
100mA for external loads. Bypass LDO with a minimum
4.7µF ceramic capacitor. When the LDOREFIN < 0.2V and
BYP voltage is 5V, the LDO bootstrap-switchover to an
internal 0.7Ω P-Channel MOSFET switch connects BYP to
LDO pin while simultaneously shutting down the internal
linear regulator. These actions bootstrap the device,
powering the loads from the BYP input voltages, rather than
through internal linear regulators from the battery. Similarly,
when the BYP = 3.3V and LDOREFIN = VCC, the LDO
bootstrap-switchover to an internal 1.5Ω P-Channel
MOSFET switch connects BYP to LDO pin while
simultaneously shutting down the internal linear regulator.
No switchover action in adjustable mode.
In Figure 68, the external 14V charge pump is driven by
LGATE1. When LGATE1 is low, D1a charged C8 sourced
from OUT1. C8 voltage is equal to OUT1 minus a diode
drop. When LGATE1 transitions to high, the charges from C8
will transfer to C₁₂ through D1b and charge it to VLGATE1
26
FN6373.6
April 29, 2010