ISL6366 Datasheet, PDF (33/44 Pages) Intersil Corporation – Dual 6-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6366
There are total of four register pins to program the system
parameters: Address OFFSET, setVID fast slew rate, boot voltage,
I_CCMAX, diode emulation option, number of phase operation at
low power mode, and temperature compensation, as
summarized in Table 9. Prior to the soft-start, the system
parameters are stored in the SVID data registers of 0C, 0D, 0E,
and 0F, respectively, as shown in Table 10. They are reset by
Enable or VCC POR. In addition, data is available to verify the
system setting over a high volume production. A design
worksheet to select these pairs of resistors is available for use.
Please contact Intersil Application support at
www.intersil.com/design/.
As an example, Table 11 shows the R_UP and R_DW values of each
pin for a specific system design; DATA for corresponding registers
can be read out via SVID’s Get(reg) command. In addition, as
shown in Table 12, some tie-high and tie-low options are for easy
programming and can also be used to validate the VR operation
during In-Circuit Test (ICT). For instance, when the system boot
voltage is required at zero Volts, the BT_XX or BTS_XX pin can be
tied to GND or VCC, prior to Enable, to get a known boot voltage
to check VR operation with ICT.
CODE
NAME
TABLE 9. SYSTEM PARAMETER DESCRIPTION
DESCRIPTION
RANGE
ADDR
VR0/1 Address offset
(VR0 and VR1 Are In Operation)
0/1, 2/3 to 6/7
VR0 Address offset (PWMS = VCC,
FSS_DRPS = 1 MΩ to GND)
0, 2, 4, 6
VR0 Address offset (PWMS=VCC,
FSS_DRPS = 1 MΩ to VCC)
VR1 Address offset (PWM1 = VCC)
8,A,C
1, 3, 5, 7
BT
BTS
FDVID
VR0 Boot Voltages
(R_{FS_DRP} TIED GND)
VR0 Boot Voltages
(R_{FS_DRP} TIED VCC)
VR1 Boot Voltages
(R_{FSS_DRPS} TIED GND)
VR1 Boot Voltages
(R_{FSS_DRPS} TIED VCC)
setVID Fast Slew Rate for VR0
0, 0.9, 1.0, 1.1V
0,1.2, 1.35, 1.5V
0, 0.9, 1.0, 1.1V
0, 0.85, 0.925, 1.05V
10mV/µs, 20mV/µs
DE
Diode Emulation Option of VR0 Enable, or Disable
DES
Diode Emulation Option of VR1
Enable, or Disable
TMAX Maximum Operating Temperature +90°C to +120°C
(5°C/Step)
IMAX
IMAXS
NPSI
I_CCMAX of VR0
(5A/step)
15-165A (1:4-Phase);
105-255A (5:6-Phase)
I_CCMAX of VR1
(R_{FSS_DRPS} TIED GND)
I_CCMAX of VR1
(R_{FSS_DRPS} TIED VCC)
Number of Operational Phases in
PSI1/2/3/Decay States
20A, 25A, 30A, 35A
15A, 20A, 25A, 30A
1 or 2-Phase
TABLE 9. SYSTEM PARAMETER DESCRIPTION (Continued)
CODE
NAME
DESCRIPTION
RANGE
TCOMP
Mismatching Temperature OFF, +13°C to +43.2°C
Compensation between sensing
element and NTC for VR0
TCOMPS
Mismatching Temperature OFF, +13°C to +43.2°C
Compensation between sensing
element and NTC for VR1
TABLE 10. SYSTEM DATA REGISTER LOCATION
REGISTER PIN NAME
DATA REGISTER CODE
ADDR_IMAXS_TMAX
0C
BTS_DES_TCOMPS
0D
BT_FDVID_TCOMP
0E
NPSI_DE_IMAX
0F
TABLE 11. DESIGN EXAMPLE
REG
0C ADDR
IMAXS
TMAX
R_UP R_DW DATA
0/1
25A
+100°C 29.4kΩ 15kΩ 08h
0D
BTS
DES
TCOMPS
0.85V ENABLED +29.7°C 255kΩ 140kΩ C0h
0E
BT
FDVID TCOMP
1.1V 20mV/µs +29.7°C 10kΩ OPEN DFh
0F
NPSI
DE
IMAX
SI1
ENABLED 190A OPEN 10kΩ 00h
TABLE 12. TIE-HIGH AND TIE-LOW OPTIONS
REG
0C
ADDR
IMAXS
(R_{FSS_DRPS}:
GND/VCC)
TMAX
R_UP R_DW DATA
0/1
35A/30A +100°C 10kΩ OPEN 0h
0/1
20A/15A +95°C OPEN 10kΩ 1Fh
6/7
35A/30A +100°C 499kΩ OPEN C0h
6/7
20A/15A +95°C OPEN 499kΩ DFh
BTS
(R_{FSS_DRPS}:
0D GND/VCC)
DES
TCOMPS
1.1V/1.5V DISABLED +29.7°C OPEN 10kΩ 00h
1.1V/1.5V ENABLED +29.7°C 10kΩ OPEN 1Fh
0
DISABLED +29.7°C OPEN 499kΩ C0h
0
ENABLED +29.7°C 499kΩ OPEN DFh
33
FN6964.0
January 3, 2011