ISL6366 Datasheet, PDF (26/44 Pages) Intersil Corporation – Dual 6-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications

ISL6366
TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued)
VOLTAGE
OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX (mV)
1 1 0 1 1 0 1 0 D A -190
1 1 0 1 1 0 1 1 D B -185
1 1 0 1 1 1 0 0 D C -180
1 1 0 1 1 1 0 1 D D -175
1 1 0 1 1 1 1 0 D E -170
1 1 0 1 1 1 1 1 D F -165
1 1 1 0 0 0 0 0 E 0 -160
1 1 1 0 0 0 0 1 E 1 -155
1 1 1 0 0 0 1 0 E 2 -150
1 1 1 0 0 0 1 1 E 3 -145
1 1 1 0 0 1 0 0 E 4 -140
1 1 1 0 0 1 0 1 E 5 -135
1 1 1 0 0 1 1 0 E 6 -130
1 1 1 0 0 1 1 1 E 7 -125
1 1 1 0 1 0 0 0 E 8 -120
1 1 1 0 1 0 0 1 E 9 -115
1 1 1 0 1 0 1 0 E A -110
1 1 1 0 1 0 1 1 E B -105
1 1 1 0 1 1 0 0 E C -100
1 1 1 0 1 1 0 1 E D -95
1 1 1 0 1 1 1 0 E E -90
1 1 1 0 1 1 1 1 E F -85
1 1 1 1 0 0 0 0 F 0 -80
1 1 1 1 0 0 0 1 F 1 -75
1 1 1 1 0 0 1 0 F 2 -70
1 1 1 1 0 0 1 1 F 3 -65
1 1 1 1 0 1 0 0 F 4 -60
1 1 1 1 0 1 0 1 F 5 -55
1 1 1 1 0 1 1 0 F 6 -50
1 1 1 1 0 1 1 1 F 7 -45
1 1 1 1 1 0 0 0 F 8 -40
1 1 1 1 1 0 0 1 F 9 -35
1 1 1 1 1 0 1 0 F A -30
1 1 1 1 1 0 1 1 F B -25
1 1 1 1 1 1 0 0 F C -20
1 1 1 1 1 1 0 1 F D -15
1 1 1 1 1 1 1 0 F E -10
1 1 1 1 1 1 1 1 F F -5
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output voltage
on load current is often termed “droop” or “load line” regulation.
By adding a well controlled output impedance, the output voltage
can effectively be level shifted in a direction, which works to
achieve the load-line regulation required by these
manufacturers.
In other cases, the designer may determine that a more cost-
effective solution can be achieved by adding droop. Droop can
help to reduce the output-voltage spike that results from fast
load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL of the
output capacitors selected. By positioning the no-load voltage
level near the upper specification limit, a larger negative spike
can be sustained without crossing the lower limit. By adding a
well controlled output impedance, the output voltage under load
can effectively be level shifted down so that a larger positive
spike can be sustained without crossing the upper specification
limit.
As shown in Figure 14, a current proportional to the average
current of all active channels, I_AVG, flows from FB through a load-
line regulation resistor R_FB. The resulting voltage drop across
R_FB is proportional to the output current, effectively creating an
output voltage droop with a steady-state value defined, as shown
in Equation 13:
V_DROOP = I_AVG ⋅ R_FB
(EQ. 13)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 13 with the appropriate sample
current expression defined by the current sense method
employed, as shown in Equation 14:
V_OUT
=
V_R
E
F
–
⎛
⎜
⎝
-I-^L---^O----^A----^D--
N
------^R----^X-------
R_ISEN
⎞
R _{F B⎠⎟}
(EQ. 14)
where V_REF is the reference voltage (DAC), I_LOAD is the total
output current of the converter, R_ISEN is the sense resistor
connected to the ISEN+ pin, and R_FB is the feedback resistor, N is
the active channel number, and R_X is the DCR, or R_SENSE
depending on the sensing method.
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 15:
R_LL
=
--R----^F----^B--
N
------^R----^X-------
R_ISEN
(EQ. 15)
The major regulation error comes from the current sensing
elements. To improve load-line regulation accuracy, a tight DCR
tolerance of inductor or a precision sensing resistor should be
considered.
Output-Voltage Offset Programming
The output voltage can be margined in ±5mV steps between
-640mV and 635mV, as shown in Table 5, via SVID set OFFSET
command (33h). The minimum offset step is ±5mV. For a finer
than 5mV offset, a large ratio resistor divider can be placed on
26
FN6964.0
January 3, 2011