ISL6322 Datasheet, PDF (33/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are the number of upper and lower MOSFETs per
phase, respectively; N_PHASE is the number of active
phases. The I_Q*VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
R_HI1
R_LO1
PHASE
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
and R_G2) and the internal gate resistors (R_GI1 and R_GI2) of
the MOSFETs. Figures 19 and 20 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P_DR, can be roughly
estimated with Equation 31.
Inductor DCR Current Sensing Component
Selection
The ISL6322 senses each individual channel’s inductor
current by detecting the voltage across the output inductor
DCR of that channel (as described in “Continuous Current
Sampling” on page 13). As Figure 21 illustrates, an R-C
network is required to accurately sense the inductor DCR
voltage and convert this information into a current, which is
proportional to the total output current. The time constant of
this R-C network must match the time constant of the
inductor L/DCR.
MOSFET
DRIVER
V_IN
UGATE(n)
LGATE(n)
IL
L
DCR
INDUCTOR
V_L(s)
V_C(s)
R₁
C₁
V_OUT
C_OUT
ISL6322 INTERNAL CIRCUIT
R_2*
I_n
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P_{DR_UP}, the lower drive path resistance,
P_{DR_UP}, and in the boot strap diode, P_BOOT. The rest of the
P_DR = P_{DR_UP} + P_{DR_LOW} + P_BOOT + (I_Q ⋅ VCC)
P_BOOT
=
-^P----^Q----^g----^_--^Q-----¹-
3
(EQ. 31)
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
R^-----_L^---_O^-----₁^{R----+-L---O-}R^----1-_E^----_X^----_T^---₁^- _{⎠⎟⎞}
⋅
P_{-----Q----g----_--Q-----1-}
3
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
⋅ ^P-----^Q----^g----^_---^Q----²-
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
power will be dissipated by the external gate resistors (R_G1
SAMPLE
+
-
I_SEN
V_C(s)
R_ISEN
ISEN-(n)
ISEN+(n)
*R₂ is OPTIONAL
FIGURE 21. DCR SENSING CONFIGURATION
The R-C network across the inductor also sets the
overcurrent trip threshold for the regulator. Before the R-C
components can be selected, the desired overcurrent
protection level should be chosen. The minimum overcurrent
trip threshold the controller can support is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, I_OCP,min, use
Equation 32, where N is the number of active channels, and
DCR is the individual inductor’s DCR.
I_{OCP, min}
=
0_----._--0_---3_---7_----5_----⋅_---N_---
DCR
(EQ. 32)
The overcurrent trip level of the ISL6322 cannot be set any
lower then the I_OCP,min level calculated above. If the
minimum overcurrent trip level is desired, do the
33
FN6328.0
August 21, 2006