ISL6322 Datasheet, PDF (25/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TDC. The typical value
for TDC can range between 1.5ms and 3.0ms.
Pre-Biased Soft-Start
The ISL6322 also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
EN (5V/DIV)
T1 T2
T3
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6322-BASED
MULTIPHASE CONVERTER
Fault Monitoring and Protection
The ISL6322 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6322 is regulating the
output voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied to a +5V source
through a resistor.
VDAC
I²C OVP
REGISTER
VRSEL
+175mV,
+250mV,
+350mV
V_OVP
-
OCL
+
170μA
I₁
REPEAT FOR
EACH CHANNEL
-
OCP
+
125μA
I_AVG
SOFT-START, FAULT
AND CONTROL LOGIC
VSEN
+
x1
-
RGND
-
OV
+
-
UV
+
PGOOD
VDIFF
0.60 x DAC _{ISL6322 INTERNAL CIRCUITRY}
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, EN_PH4, POR, or one of the no-CPU VID codes. In the
event of an overvoltage or overcurrent condition, the
controller latches off and PGOOD will not return high until
after a successful soft-start. In the case of an undervoltage
event, PGOOD will return high when the output voltage
returns to within the undervoltage.
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Overvoltage Protection
The ISL6322 constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level
actions are taken by the ISL6322 to protect the
microprocessor load. The overvoltage protection trip level
changes depending on what mode of operation the controller
is in and what state the I²C registers and the VRSEL pin are
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FN6328.0
August 21, 2006