ISL6322 Datasheet, PDF (24/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
5. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
For the Intel VR10 and VR11 modes of operation, the
soft-start sequence is composed of four periods, as shown in
Figure 11. Once the ISL6322 is released from shutdown and
soft-start begins (as described in the Enable and Disable
section), the controller will have fixed delay period TD1. After
this delay period, the VR will begin first soft-start ramp until
the output voltage reaches 1.1V VBOOT voltage. Then, the
controller will regulate the VR voltage at 1.1V for another
fixed period TD3. At the end of TD3 period, ISL6322 will
read the VID signals. If the VID code is valid, ISL6322 will
initiate the second soft-start ramp until the output voltage
reaches the VID voltage plus/minus any offset or droop
voltage.
The soft-start time is the sum of the four periods as shown in
Equation 17.
T_SS = TD1 + TD2 + TD3 + TD4
(EQ. 17)
During TD2 and TD4, ISL6322 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on the following equations:
TD2
=
1----.--1----⋅_{---R-----S----S--}
6.25 ⋅ 25
(
μ
s
)
(EQ. 18)
TD4 = --⁽--V-----^V----^I-^D-6----.-^–_{2----51----.-â‹}^1--2--)--5---^â‹---R-----^S---^S-- (μs)
(EQ. 19)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
NOTE: If the SS pin is grounded, the soft-start ramp in TD2
and TD4 will be defaulted to a 6.25mV step frequency of
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TD5. The typical value
for TD5 is 440µs.
VOUT, 500mV/DIV
TDA
TDB
EN_VTT
TDC
VOUT, 500mV/DIV
TD1
TD2 TD3 TD4 TD5
EN_VTT
PGOOD
500µs/DIV
FIGURE 11. INTEL SOFT-START WAVEFORMS
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
24
PGOOD
500µs/DIV
FIGURE 12. AMD SOFT-START WAVEFORMS
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period TDA. After this delay period the ISL6322 will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 20.
TDB
=
------------¹-------------
330 × 10³
⋅
⎛
⎝
0^----.^-V0----V0^---6^-I--D2^----5^{--⎠⎞}
(EQ. 20)
FN6328.0
August 21, 2006